公开(公告)号：US06713359B1

公开(公告)日：2004-03-30

申请号：US09564191

申请日：2000-05-04

申请人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

发明人： Ichiro Mizushima ,  Shigehiko Saida ,  Takeo Furuhata ,  Yoshitaka Tsunashima

IPC分类号： H01L21336

CPC分类号： H01L29/66477 ,  H01L21/28052 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/665

摘要： SiGe or SiC films are selectively grown on source/drain regions, followed by selectively growing silicon. A monocrystalline film having a high dislocation density or a polycrystalline film can be grown in growing the silicon film by making the C or Ge concentration higher than a predetermined level. The silicon layer on each of the source/drain regions is not monocrystalline or, even if monocrystalline, has a high density of dislocation. Therefore, the silicon film formed thereon is in the form of a monocrystalline silicon film having a high dislocation density or a polycrystalline silicon film. It is possible to suppress an impurity diffusion to reach a deep region caused by channeling of ions generated in the doping step by means of an ion implantation.

摘要翻译： SiGe或SiC膜选择性地在源极/漏极区域上生长，随后选择性地生长硅。 通过使C或Ge浓度高于预定水平，可以在生长硅膜时生长具有高位错密度的单晶膜或多晶膜。 源极/漏极区域中的每一个上的硅层不是单晶的，即使单晶也具有高密度的位错。 因此，其上形成的硅膜是具有高位错密度的单晶硅膜或多晶硅膜的形式。 可以通过离子注入来抑制在掺杂步骤中产生的离子的沟道引起的深度区域的杂质扩散。

公开(公告)号：US20070215958A1

公开(公告)日：2007-09-20

申请号：US11798593

申请日：2007-05-15

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L29/94

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07060555B2

公开(公告)日：2006-06-13

申请号：US10895144

申请日：2004-07-21

申请人： Masayuki Tanaka ,  Shigehiko Saida ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Shigehiko Saida ,  Yoshitaka Tsunashima

IPC分类号： H01L21/336

CPC分类号： H01L21/0217 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10873 ,  H01L2924/0002 ,  H01L2924/00

摘要： Hexachlorodisilane (Si2Cl6) is used as a Si raw material for forming a silicon nitride film that can be widely different in the etching rate from a silicon oxide film. The silicon nitride film is formed by an LPCVD method.

公开(公告)号：US06772045B2

公开(公告)日：2004-08-03

申请号：US10231019

申请日：2002-08-30

申请人： Shuji Katsui ,  Masayuki Tanaka ,  Masaki Kamimura ,  Hiroshi Akahori ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Shigehiko Saida ,  Yoshitaka Tsunashima ,  Yuuichi Mikata

发明人： Shuji Katsui ,  Masayuki Tanaka ,  Masaki Kamimura ,  Hiroshi Akahori ,  Ichiro Mizushima ,  Takashi Nakao ,  Akihito Yamamoto ,  Shigehiko Saida ,  Yoshitaka Tsunashima ,  Yuuichi Mikata

IPC分类号： G06F1900

CPC分类号： H04L12/66 ,  Y10S438/905

摘要： A system for determining dry cleaning timing, includes: a manufacturing apparatus configured to process materials assigned by a sequence of lots; an apparatus controller configured to control the manufacturing apparatus and obtaining operational conditions of the manufacturing apparatus as apparatus information; a lot information input terminal configured to obtain process conditions of one of the lots as lot information; an apparatus information storage unit configured to store the apparatus information from the apparatus controller as an apparatus information database; a lot information storage unit configured to store the lot information from the lot information input terminal as a lot information database; and a cleaning determination unit configured to determine timing to perform a dry cleaning of the manufacturing apparatus based on the apparatus information database and the lot information database.

摘要翻译： 一种用于确定干洗时间的系统，包括：制造装置，被配置为处理由批次序列分配的材料; 设备控制器，其被配置为控制所述制造设备并获得所述制造设备的操作条件作为设备信息; 许多信息输入终端，被配置为获取所述批中的一个的处理条件作为批量信息; 设备信息存储单元，被配置为将来自设备控制器的设备信息作为设备信息数据库存储; 许多信息存储单元被配置为将来自批次信息输入终端的批量信息作为批次信息数据库存储; 以及清洁确定单元，被配置为基于装置信息数据库和批次信息数据库来确定对制造装置进行干洗的定时。

公开(公告)号：US06284583B1

公开(公告)日：2001-09-04

申请号：US09105024

申请日：1998-06-26

申请人： Shigehiko Saida ,  Yoshitaka Tsunashima

发明人： Shigehiko Saida ,  Yoshitaka Tsunashima

IPC分类号： H01L218249

CPC分类号： H01L21/3185 ,  C23C16/0218 ,  C23C16/0272 ,  C23C16/345 ,  H01L27/10852 ,  H01L27/10861

摘要： A semiconductor device comprises a semiconductor substrate and a silicon nitride film formed on the semiconductor substrate. The silicon nitride film is substantially free from an Si—H bond and has an Si—H density per unit area of 1×1015 cm−2 or less.

摘要翻译： 半导体器件包括形成在半导体衬底上的半导体衬底和氮化硅膜。 氮化硅膜基本上不含Si-H键，并且每单位面积的Si-H密度为1×10 15 cm -2以下。

公开(公告)号：US06893928B2

公开(公告)日：2005-05-17

申请号：US10390046

申请日：2003-03-18

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Toshihiko Iinuma ,  Kiyotaka Miyano

IPC分类号： H01L29/78 ,  H01L21/324 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/66583 ,  H01L21/324 ,  H01L21/76229 ,  H01L21/76232 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7831 ,  H01L29/78639

摘要： To provide a cavity in the portion of the silicon substrate which lies beneath the channel region of the MOS transistor.

摘要翻译： 在硅衬底的位于MOS晶体管的沟道区之下的部分提供空腔。

公开(公告)号：US06552380B1

公开(公告)日：2003-04-22

申请号：US09531537

申请日：2000-03-20

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima

IPC分类号： H01L31119

CPC分类号： H01L21/30604 ,  H01L27/10861 ,  H01L28/60 ,  H01L29/66181

摘要： A deep trench is formed in a silicon substrate. The inner surface of the trench is next coated with a thin polycrystalline silicon film (liner film) so as not to close the trench. A silicon germanium film (node electrode) is then formed on the thin polycrystalline silicon film so as not to close the trench. Next, a heat treatment is performed on the silicon germanium film thereby to flow only the silicon germanium so that the trench is filled.

公开(公告)号：US6100132A

公开(公告)日：2000-08-08

申请号：US106082

申请日：1998-06-29

申请人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

发明人： Tsutomu Sato ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Junichiro Iba

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/909

摘要： A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

摘要翻译： 半导体器件包括在其表面上具有沟槽的半导体衬底和嵌入沟槽内部的嵌入构件。 虽然当垂直于沟槽深度方向的第一平面切割沟槽的部分被定义为第一部分，并且当垂直于沟槽深度方向的第二平面切割沟槽的部分时 并且比所述第一平面更靠近所述沟槽的底部被限定为第二部分，所述第一部分的面积小于所述第二部分的面积，并且所述第一部分的最小曲率半径小于所述第一部分的最小半径 第二部分的曲率。 结果，可以减小进入沟槽底部的电场的浓度。

公开(公告)号：US07507634B2

公开(公告)日：2009-03-24

申请号：US11812490

申请日：2007-06-19

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。

公开(公告)号：US07235456B2

公开(公告)日：2007-06-26

申请号：US11340594

申请日：2006-01-27

申请人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

发明人： Tsutomu Sato ,  Mie Matsuo ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Shinichi Takagi

IPC分类号： H01L21/764 ,  H01L27/12

CPC分类号： H01L27/10805 ,  B82Y20/00 ,  G02B6/122 ,  G02B6/1225 ,  G02B2006/12097 ,  H01L21/3247 ,  H01L21/7624 ,  H01L21/76283 ,  H01L21/76289 ,  H01L21/764 ,  H01L21/84 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0657 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78639

摘要： To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

摘要翻译： 通过在半导体衬底的表面上二维地形成沟槽，然后对半导体衬底进行热处理，将多个沟槽改变为一个平坦的空间。