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141 条记录 (耗时 0.034 秒)

    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
    11.
    发明申请
    Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process 失效
    在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法

    公开(公告)号：US20050191855A1

    公开(公告)日：2005-09-01

    申请号：US10788912

    申请日：2004-02-27

    申请人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Jung-Chih Tsao ,  Chi-Wen Liu ,  Jchung-Chang Chen ,  Shih-Tzung Chang ,  Shih-Ho Lin ,  Yu-Ku Lin ,  Ying-Lang Wang

    IPC分类号： H01L21/44 ,  H01L21/768

    CPC分类号： H01L21/76844 ,  H01L21/76807 ,  H01L21/76862 ,  H01L21/76865

    摘要： A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.

    摘要翻译： 一种用于形成具有改善的铜迁移阻力和改善的电阻率的铜双镶嵌的方法，包括提供包括由中间蚀刻停止层分隔的上和下介电绝缘层的半导体晶片; 形成延伸通过上下介电绝缘层的厚度的双镶嵌开口，其中上沟槽线部分延伸穿过上介电绝缘层的厚度并部分地穿过中蚀刻停止层; 毯子沉积包括难熔金属和难熔金属氮化物中的至少一种的阻挡层，以便排列双镶嵌开口; 对双镶嵌开口执行远程等离子体蚀刻处理以去除阻挡层的底部以露出下面的导电区域; 并且用铜填充双镶嵌开口以提供基本平坦的表面。

    Semiconductor device contact structures and methods for making the same
    15.
    发明授权
    Semiconductor device contact structures and methods for making the same 有权
    半导体器件接触结构及其制造方法

    公开(公告)号：US08518819B2

    公开(公告)日：2013-08-27

    申请号：US13049049

    申请日：2011-03-16

    申请人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    发明人： Shih Chieh Chang ,  Chih-Chung Chang ,  Kei-Wei Chen ,  Ying-Lang Wang

    IPC分类号： H01L23/52 ,  H01L21/768

    CPC分类号： H01L23/53266 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

    摘要翻译： 半导体接触结构和方法提供延伸穿过电介质材料并提供与包括硅化物材料和非硅化物材料（例如掺杂硅）的多个不同下层材料的接触的接触结构。 接触结构包括使用多步电离金属等离子体（IMP）沉积操作形成的下复合层。 下部IMP膜以高AC偏压功率形成，随后以较低的AC偏压功率形成上部IMP膜。 复合层可以由钛形成。 在复合层上形成另一层作为衬垫，并且衬垫层可以有利地使用CVD形成，并且可以是TiN。 诸如钨或铜的导电插塞材料填充接触开口。

    Current-leveling electroplating/electropolishing electrode
    18.
    发明申请
    Current-leveling electroplating/electropolishing electrode 有权
    电流调平电镀/电解抛光电极

    公开(公告)号：US20060086609A1

    公开(公告)日：2006-04-27

    申请号：US10971836

    申请日：2004-10-22

    申请人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

    发明人： Shih-Chieh Chang ,  Ying-Lang Wang ,  Kei-Wei Chen ,  Shih-Ho Lin ,  Chun-Chang Chen

    IPC分类号： C25B11/02

    CPC分类号： H01L21/2885 ,  C25D17/001 ,  C25D17/12 ,  Y10T29/49208 ,  Y10T29/53204

    摘要： A current-leveling electrode for improving electroplating and electrochemical polishing uniformity in the electrochemical plating or electropolishing of metals on a substrate is disclosed. The current-leveling electrode includes a base electrode and at least one sub-electrode carried by the base electrode. The at least one sub-electrode has a width which is less than a width of the base electrode to impart a generally tapered, stepped or convex configuration to the current-leveling electrode.

    摘要翻译： 公开了一种用于改善电化学电镀中的电镀和电化学抛光均匀性的电流调节电极或对基底上的金属的电解抛光。 电流调平电极包括基极和由基极承载的至少一个子电极。 所述至少一个子电极的宽度小于所述基极的宽度，以赋予所述电流调平电极大致锥形，阶梯形或凸形的构造。

    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch
    19.
    发明申请
    Forming Seed Layer in Nano-Trench Structure Using Net Deposition and Net Etch 审中-公开
    使用净沉积和净蚀刻在纳米沟槽结构中形成种子层

    公开(公告)号：US20090127097A1

    公开(公告)日：2009-05-21

    申请号：US11941435

    申请日：2007-11-16

    申请人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    发明人： Kei-Wei Chen ,  Shih-Ho Lin ,  Yu-Sheng Wang ,  Szu-An Wu ,  Ying-Lang Wang

    IPC分类号： C23C14/00

    CPC分类号： C23C14/345 ,  C23C14/046 ,  H01L21/76862 ,  H01L21/76873

    摘要： A method of forming an integrated circuit structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a net deposition step to form a seed layer having a portion in the opening, wherein the net deposition step comprises a first deposition and a first etching; performing a net etch step to the seed layer, wherein the net etch step comprises a first etching and a first deposition, wherein a portion of the seed layer remains after the net etch step; and growing a conductive material on the seed layer to fill a remaining portion of the opening.

    摘要翻译： 形成集成电路结构的方法包括形成电介质层; 在介电层中形成开口; 执行净沉积步骤以形成具有在开口中的一部分的种子层，其中所述净沉积步骤包括第一沉积和第一蚀刻; 对所述种子层进行净蚀刻步骤，其中所述净蚀刻步骤包括第一蚀刻和第一沉积，其中所述种子层的一部分在所述净蚀刻步骤之后保留; 以及在种子层上生长导电材料以填充开口的剩余部分。

    Oxidation-free copper metallization process using in-situ baking
    20.
    发明授权
    Oxidation-free copper metallization process using in-situ baking 有权
    无氧化铜金属化工艺采用原位烘烤

    公开(公告)号：US08470390B2

    公开(公告)日：2013-06-25

    申请号：US11972785

    申请日：2008-01-11

    申请人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    发明人： Yu-Sheng Wang ,  Shih-Ho Lin ,  Kei-Wei Chen ,  Szu-An Wu ,  Ying-Lang Wang

    IPC分类号： B05D5/12 ,  C23C14/00

    CPC分类号： H01L21/76814 ,  H01L21/02063 ,  H01L21/76828 ,  H01L21/76843

    摘要： A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.

    摘要翻译： 形成集成电路结构的方法包括提供基板; 在衬底上形成金属特征; 在金属特征上形成介电层; 并在介电层中形成开口。 金属特征的至少一部分通过开口露出。 相应地，在金属特征的暴露部分上形成氧化物层。 该方法还包括在具有真空环境的生产工具中进行氧化物去除工艺以去除氧化物层。 在形成开口的步骤和氧化物去除工艺之间，对生产工具外部的金属特征没有进行额外的氧化物去除处理。 该方法还包括在生产工具中在开口中形成扩散阻挡层，并在扩散阻挡层上形成种子层。