公开(公告)号：US06995415B2

公开(公告)日：2006-02-07

申请号：US10475115

申请日：2003-02-14

Applicant: Hisashi Ogawa ,  Hiroaki Nakaoka ,  Atsuhiro Kajiya ,  Shin Hashimoto ,  Kyoko Egashira

Inventor： Hisashi Ogawa ,  Hiroaki Nakaoka ,  Atsuhiro Kajiya ,  Shin Hashimoto ,  Kyoko Egashira

IPC: H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897

Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract translation: 存储单元晶体管和平面电容器设置在存储区域中，CMOS器件的两个晶体管都设置在逻辑电路区域中。 平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离层12a共同的沟槽上，并且沟槽的上部填充有电容电介质15和板电极16b。 形成作为存储节点的n型扩散层19，其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离层12a重叠的区域。 可以增加用作电容器的基板的一部分的面积，而不增加基板面积。

公开(公告)号：US5468983A

公开(公告)日：1995-11-21

申请号：US203627

申请日：1994-03-01

Applicant: Junji Hirase ,  Shin Hashimoto

Inventor： Junji Hirase ,  Shin Hashimoto

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L33/00

CPC classification number: H01L27/108 ,  H01L27/105

Abstract: In a semiconductor device, an outer peripheral part of an integrated circuit region separated by an insulation part is defined as a dummy cell region and a center part except the outer peripheral part of the integrated circuit region is defined as an active cell region. Memory cells such as DRAM, SRAM, EEPROM, mask ROM are formed in the active cell region. In the integrated circuit region, plural cell forming regions are provided which are respectively defined by an isolation. Active cells each having a field effect semiconductor element are provided in a region included in the active cell region of each cell forming region. Dummy cells each having an element inoperable as an semiconductor element are provided in a region included in the dummy cell region of each cell forming region. At last one of dummy cells is made to be a P-N lacking dummy cell having a semiconductor element in construction including at least a gate and excluding at least one of P-N junction parts from the same construction as the field effect semiconductor element in the active cells. All dummy cells may be the P-N lacking dummy cells. Thereby, insulation defects through the P-N lacking dummy cell due to disturbance of gate pattern and the like in the dummy cell region is prevented.

Abstract translation: 在半导体器件中，由绝缘部分隔开的集成电路区域的外周部分被定义为虚设单元区域，并且除了集成电路区域的外周部分之外的中心部分被定义为有源单元区域。 诸如DRAM，SRAM，EEPROM，掩模ROM的存储单元形成在活动单元区域中。 在集成电路区域中，设置多个单元形成区，分别由隔离限定。 每个具有场效应半导体元件的有源电池被提供在每个电池形成区域的有源电池区域中包括的区域中。 每个具有不可用作半导体元件的元件的虚拟单元设置在每个单元形成区域的虚拟单元区域中包括的区域中。 最后一个虚设单元被制成为具有至少具有栅极并且从与活性单元中的场效应半导体元件相同结构的P-N结部分中的至少一个排列的至少一个半导体元件的P-N缺乏的虚设单元。 所有虚拟细胞可能是缺乏伪细胞的P-N。 因此，防止了由于虚设单元区域中的栅极图案等的干扰而导致的缺乏虚设单元的P-N的绝缘缺陷。

公开(公告)号：US5300814A

公开(公告)日：1994-04-05

申请号：US915898

申请日：1992-07-17

Applicant: Susumu Matsumoto ,  Shin Hashimoto ,  Toshio Yamada ,  Yoshiro Nakata

Inventor： Susumu Matsumoto ,  Shin Hashimoto ,  Toshio Yamada ,  Yoshiro Nakata

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L23/528 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L23/48 ,  H01L29/46

CPC classification number: H01L27/105 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S257/92

Abstract: A semiconductor device comprising a semiconductor substrate, a plurality of memory cell regions each having a plurality of memory cells disposed on the semiconductor substrate, a word line formed in a first level above the semiconductor substrate, a bit line formed in a second level above the first level, and a backing line having a lower resistance than the word line and formed in a third level above the second level. A dummy bit line is formed in the second level outside the memory cell region so as to reduce the step formed at the periphery of the memory cell region. The dummy bit line is also used to interconnect the word line and the backing line so that an electrical connection therebetween is stabilized.

Abstract translation: 一种半导体器件，包括半导体衬底，多个存储单元区域，每个存储单元区域具有设置在半导体衬底上的多个存储单元，形成在半导体衬底上方的第一级中的字线，形成在第二级上方的位线 第一级和背衬线，其具有比字线更低的电阻并且形成在高于第二级的第三级中。 在存储单元区域外部的第二电平中形成虚拟位线，以便减小形成在存储单元区域周边的台阶。 虚拟位线也用于互连字线和背衬线，使得它们之间的电连接稳定。

公开(公告)号：US08653561B2

公开(公告)日：2014-02-18

申请号：US13038071

申请日：2011-03-01

Applicant: Shin Hashimoto ,  Katsushi Akita ,  Yoshiyuki Yamamoto ,  Masaaki Kuzuhara ,  Norimasa Yafune

Inventor： Shin Hashimoto ,  Katsushi Akita ,  Yoshiyuki Yamamoto ,  Masaaki Kuzuhara ,  Norimasa Yafune

IPC: H01L21/02 ,  H01L29/778 ,  H01L21/335

CPC classification number: H01L29/66462 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/7787

Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively. A concentration of impurity in the first portion is the same as that of impurity in the second portion, and the first and second electrodes is provided on the first and second regions, respectively. The first electrode includes a drain electrode or a source electrode. An aluminum composition of the first III-nitride semiconductor is not less than 0.16, and a bandgap of the second III-nitride semiconductor being larger than that of the first III-nitride semiconductor.

Abstract translation: III族氮化物半导体电子器件包括设置在衬底的主表面上的半导体层叠体，与半导体层叠体接触的第一电极和第二电极。 半导体层叠体包括沟道层和与沟道层形成结的阻挡层。 沟道层包括含有铝作为III族构成元素的第一III族氮化物半导体，并且阻挡层包含含有铝作为III族构成元素的第二III族氮化物半导体。 包括沿主表面布置的第一，第二和第三区域以及第三区域的半导体层叠体位于第一区域和第二区域之间。 阻挡层包括分别包括在第一至第三区域中的第一至第三部分。 第一部分中的杂质浓度与第二部分中的杂质浓度相同，第一和第二电极分别设置在第一和第二区域上。 第一电极包括漏电极或源电极。 第一III族氮化物半导体的铝组成不小于0.16，并且第二III族氮化物半导体的带隙大于第一III族氮化物半导体的带隙。

公开(公告)号：US08541816B2

公开(公告)日：2013-09-24

申请号：US12740770

申请日：2008-10-28

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: H01L21/338

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/7787 ,  H01L29/872

Abstract: In a group III nitride hetero junction transistor 11a, a second AlY1InY2Ga1-Y1-Y2N layer 15 forms a hetero junction 21 with a first AlX1InX2Ga1-X1-X2N layer 13a. A first electrode 17 forms a Schottky junction with the first AlX1InX2Ga1-X1-X2N layer 13a. The first AlX1InX2Ga1-X1-X2N layer 13a and the second AlY1InY2Ga1-Y1-Y2N layer 15 are provided over a substrate 23. The electrodes 17a, 18a, and 19a include a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlX1InX2Ga1-X1-X2N layer 13a is less than 1×1017 cm−3. The dislocation density D in the second AlY1InY2Ga1-Y1-Y2N layer 15 is 1×108 cm−2. The hetero junction 21 generates a two-dimensional electron gas layer 25. These provide a low-loss gallium nitride based electronic device.

Abstract translation: 在III族氮化物异质结晶体管11a中，第二AlY1InY2Ga1-Y1-Y2N层15与第一AlX1InX2Ga1-X1-X2N层13a形成异质结21。 第一电极17与第一AlX1InX2Ga1-X1-X2N层13a形成肖特基结。 第一AlX1InX2Ga1-X1-X2N层13a和第二AlY1InY2Ga1-Y1-Y2N层15设置在衬底23上。电极17a，18a和19a分别包括源电极，栅极电极和漏电极。 第一AlX1InX2Ga1-X1-X2N层13a中的碳浓度NC13小于1×1017cm-3。 第二AlY1InY2Ga1-Y1-Y2N层15中的位错密度D为1×108cm-2。 异质结21产生二维电子气体层25.这些提供了一种低损耗氮化镓基电子器件。

公开(公告)号：US08076736B2

公开(公告)日：2011-12-13

申请号：US12518124

申请日：2008-02-12

Applicant: Masashi Hayashi ,  Shin Hashimoto

Inventor： Masashi Hayashi ,  Shin Hashimoto

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/66068

Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.

Abstract translation: 根据本发明的半导体器件包括：碳化硅半导体衬底（1），其包括碳化硅层（2）; 设置在碳化硅层（2）中的高浓度杂质区（4）; 与高浓度杂质区（4）电连接的欧姆电极（9）。 与高浓度杂质区电连接的沟道区域; 设置在所述沟道区上的栅极绝缘层（14） 以及设置在所述栅极绝缘层（14）上的栅电极（7）。 欧姆电极（9）含有钛，硅和碳的合金，栅电极（7）含有硅化钛。

公开(公告)号：US07582394B2

公开(公告)日：2009-09-01

申请号：US10957599

申请日：2004-10-05

Applicant: Kenji Noda ,  Shin Hashimoto

Inventor： Kenji Noda ,  Shin Hashimoto

IPC: G03F1/00 ,  H01L21/00

CPC classification number: G03F1/36

Abstract: A photomask includes, on a translucent substrate, three or more first light-shielding portions each in insular shape having a property of shielding exposure light and spaced equidistantly, a second light-shielding portion having a property of shielding the exposure light and formed to connect the adjacent first light-shielding portions, and first light-transmitting portions each in slit shape having a property of transmitting the exposure light and formed to be surrounded with the first and second light-shielding portions. The second light-shielding portion is formed to contain a point located equidistantly from the three or more first light-shielding portions.

Abstract translation: 一种光掩模在透光性基板上具有三个以上的具有隔离曝光光等间隔的特性的具有岛状的三个以上的第一遮光部，具有屏蔽曝光光的特性的第二遮光部，形成为连接 相邻的第一遮光部和具有透射曝光光的特性的狭缝状的第一透光部，形成为被第一和第二遮光部包围。 第二遮光部形成为包含与三个以上的第一遮光部等距离地设置的点。

公开(公告)号：US20090194796A1

公开(公告)日：2009-08-06

申请号：US11569798

申请日：2006-03-01

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Tatsuya Tanabe ,  Kouhei Miura ,  Takashi Sakurada

IPC: H01L29/812 ,  H01L29/78 ,  H01L29/207

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/2003 ,  H01L29/8611 ,  H01L29/872

Abstract: Affords epitaxial substrates for vertical gallium nitride semiconductor devices that have a structure in which a gallium nitride film of n-type having a desired low carrier concentration can be provided on a gallium nitride substrate of n type. A gallium nitride epitaxial film (65) is provided on a gallium nitride substrate (63). A layer region (67) is provided in the gallium nitride substrate (63) and the gallium nitride epitaxial film (65). An interface between the gallium nitride substrate (43) and the gallium nitride epitaxial film (65) is positioned in the layer region (67). In the layer region (67), a peak value of donor impurity along an axis from the gallium nitride substrate (63) to the gallium nitride epitaxial film (65) is 1×1018 cm−3 or more. The donor impurity is at least either silicon or germanium.

Abstract translation: 提供具有其中可以在n型氮化镓衬底上提供具有期望的低载流子浓度的n型氮化镓膜的结构的垂直氮化镓半导体器件的外延衬底。 氮化镓外延膜（65）设置在氮化镓衬底（63）上。 在氮化镓衬底（63）和氮化镓外延膜（65）中设置一个层区（67）。 氮化镓衬底（43）和氮化镓外延膜（65）之间的界面位于层区（67）中。 在层区域（67）中，施主杂质沿着氮化镓衬底（63）到氮化镓外延膜（65）的轴的峰值为1×10 18 cm -3以上。 供体杂质至少是硅或锗。

公开(公告)号：US20090189190A1

公开(公告)日：2009-07-30

申请号：US11571156

申请日：2006-03-03

Applicant: Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

Inventor： Shin Hashimoto ,  Makoto Kiyama ,  Takashi Sakurada ,  Tatsuya Tanabe ,  Kouhei Miura ,  Tomihito Miyazaki

IPC: H01L29/80 ,  H01L21/20

CPC classification number: H01L29/7787 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/66462

Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm−3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm−3.

Abstract translation: 提供具有高纯度沟道层和高电阻缓冲层的高电子迁移率晶体管。 高电子迁移率晶体管11设置有由氮化镓构成的支撑基板13，由第一氮化镓半导体构成的缓冲层15，由第二氮化镓半导体构成的沟道层17，由第三氮化镓半导体构成的半导体层19 氮化镓半导体，以及用于晶体管11的电极结构（栅电极21，源电极23和漏电极25）。第三氮化镓半导体的带隙比第二氮化镓半导体的带隙宽。 第一氮化镓半导体的碳浓度NC1为4×10 17 cm -3以上。 第二氮化镓半导体的碳浓度NC2小于4×10 16 cm -3。

公开(公告)号：US07538005B2

公开(公告)日：2009-05-26

申请号：US11714195

申请日：2007-03-06

Applicant: Kyoko Egashira ,  Shin Hashimoto

Inventor： Kyoko Egashira ,  Shin Hashimoto

IPC: H01L21/20

CPC classification number: H01L28/60 ,  H01L21/76838 ,  H01L21/76895 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is composed of: an interconnect made of a first conductive film and a second conductive film that are stacked in sequence from the interconnect underside on an insulating film formed on a substrate; and a capacitor composed of a lower capacitor electrode made of the first conductive film, a dielectric film formed on the lower capacitor electrode, and an upper capacitor electrode made of the second conductive film and formed on the dielectric film.

Abstract translation: 半导体器件由以下部分构成：由第一导电膜和第二导电膜构成的互连，其从形成在基板上的绝缘膜上的互连下侧依次层叠; 以及由第一导电膜制成的下部电容电极，形成在下部电容电极上的电介质膜和形成在该电介质膜上的由上述第二导电膜构成的上部电容电极构成的电容器。