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    FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING
    11.
    发明申请
    FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS WITH ENHANCED FLOATING GATE TO FLOATING GATE CAPACITIVE COUPLING 有权

    公开(公告)号：US20210305264A1

    公开(公告)日：2021-09-30

    申请号：US17069563

    申请日：2020-10-13

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

    IPC: H01L27/11529 ,  H01L27/11551 ,  H01L29/66 ,  H01L29/423

    Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
    13.
    发明申请
    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices 有权

    公开(公告)号：US20210272973A1

    公开(公告)日：2021-09-02

    申请号：US16803876

    申请日：2020-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  JinHo Kim ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

    IPC: H01L27/11534 ,  H01L27/11521

    Abstract: A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

    Method Of Forming Pairs Of Three-Gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps
    16.
    发明申请
    Method Of Forming Pairs Of Three-Gate Non-volatile Flash Memory Cells Using Two Polysilicon Deposition Steps 审中-公开

    公开(公告)号：US20190148529A1

    公开(公告)日：2019-05-16

    申请号：US16245069

    申请日：2019-01-10

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Chieng-Sheng Su ,  Nhan Do ,  Chunming Wang

    IPC: H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L49/02 ,  H01L27/07 ,  H01L29/08 ,  H01L29/788

    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

    Split gate non-volatile flash memory cell having metal gates
    17.
    发明授权
    Split gate non-volatile flash memory cell having metal gates 有权

    公开(公告)号：US10249631B2

    公开(公告)日：2019-04-02

    申请号：US15945161

    申请日：2018-04-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chien-Sheng Su ,  Feng Zhou ,  Jeng-Wei Yang ,  Hieu Van Tran ,  Nhan Do

    IPC: H01L29/423 ,  H01L27/11521 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11524

    Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.

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