公开(公告)号：US20140179067A1

公开(公告)日：2014-06-26

申请号：US14190635

申请日：2014-02-26

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L29/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract translation: 公开了半导体封装及其制造方法。 该制造方法包括以下步骤：提供具有与活性表面相对的活性表面和非活性表面的半导体芯片，粗糙化非活性表面的周边部分，以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分，通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上，在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合，并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。

公开(公告)号：US10199341B2

公开(公告)日：2019-02-05

申请号：US15224767

申请日：2016-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/00

Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

公开(公告)号：US20170317040A1

公开(公告)日：2017-11-02

申请号：US15224767

申请日：2016-08-01

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L23/293 ,  H01L23/3157 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/13 ,  H01L2224/02126 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/02205 ,  H01L2224/0221 ,  H01L2224/02373 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05557 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/131 ,  H01L2224/81192 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/014

Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.

公开(公告)号：US20170148761A1

公开(公告)日：2017-05-25

申请号：US15400608

申请日：2017-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

公开(公告)号：US20150035163A1

公开(公告)日：2015-02-05

申请号：US14012402

申请日：2013-08-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing a semiconductor element in a groove of a carrier; forming a dielectric layer on the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second of the carrier on a sidewall of the groove intact for the second portion to function as a supporting part. The present invention does not require formation of a silicon interposer, therefore the overall cost of the final product is much reduced.

Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将半导体元件放置在载体的凹槽中; 在所述半导体元件上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分以将所述载体的第二载体保持在所述凹槽的侧壁上，以使所述第二部分用作支撑部分。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。

公开(公告)号：US08895366B2

公开(公告)日：2014-11-25

申请号：US14190635

申请日：2014-02-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Home Huang ,  Wen-Tsung Tseng ,  Chang-Fu Lin ,  Ho-Yi Tsai ,  Cheng-Hsu Hsiao

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L29/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.

Abstract translation: 公开了半导体封装及其制造方法。 该制造方法包括以下步骤：提供具有与活性表面相对的活性表面和非活性表面的半导体芯片，粗糙化非活性表面的周边部分，以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分，通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上，在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合，并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。