公开(公告)号：US20110289510A1

公开(公告)日：2011-11-24

申请号：US13143993

申请日：2010-02-02

Applicant: Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

Inventor： Qi Lin ,  Liang Peng ,  Craig E. Hampel ,  Thomas J. Sheffler ,  Steven C. Woo ,  Bohuslav Rychlik

IPC: G06F9/46

CPC classification number: G06F12/00 ,  G06F9/3004 ,  G06F9/3834 ,  G06F12/0815

Abstract: A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available.

Abstract translation: 缓存相干协议在共享内存空间的多个处理器（或处理器核心）之间分配原子操作。 当包括修改存储在共享存储器空间中的数据的指令的原子操作被引导到不具有与数据相关联的地址的控制的第一处理器时，第一处理器发送包括指令的请求 修改数据到第二个处理器。 然后，已经具有对地址的控制的第二处理器修改数据。 此外，第一处理器可以立即进行另一个指令，而不是等待地址变得可用。

公开(公告)号：US20110286267A1

公开(公告)日：2011-11-24

申请号：US13140345

申请日：2009-10-08

Applicant: Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

Inventor： Bohuslav Rychlik ,  John Eric Linstadt ,  Brent Steven Haukness ,  Steven C. Woo

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

Abstract translation: 一种操作存储器件的方法包括接收要存储在器件中的多级单元中的第一组和第二组位。 从用于存储多级单元中的第一和第二位组的多个多级编码中选择多级编码。 每个多级编码包括用于相应多级单元的至少四个编码电平。 相应的多级编码具有与根据相应的多级编码将第一和第二组位编程到多级单元中相关联的成本。 基于相应编码的相应成本来选择多级编码。 第一和第二组位根据所选择的多级编码进行编码，以产生用于存储在设备中的编码数据，使得相应的多级单元存储来自第一和第二组位的相应位。

公开(公告)号：US20110216611A1

公开(公告)日：2011-09-08

申请号：US13111446

申请日：2011-05-19

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C8/18

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。

公开(公告)号：US07599239B2

公开(公告)日：2009-10-06

申请号：US10770150

申请日：2004-02-02

Applicant: Steven C. Woo ,  Craig E. Hampel

Inventor： Steven C. Woo ,  Craig E. Hampel

IPC: G11C5/14

CPC classification number: G11C5/02

Abstract: Systems and methods for reducing heat flux in memory systems are described. In various embodiments, heat flux reductions are achieved by manipulating the device IDs of individual memory devices that comprise a memory module. Through the various described techniques, the per-face heat flux can be desirably reduced. Further, in some embodiments, reductions in heat flux are achieved by providing control lines that operably connect memory devices on different faces of a memory module.

公开(公告)号：US20090161453A1

公开(公告)日：2009-06-25

申请号：US12049928

申请日：2008-03-17

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C7/22

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US07222224B2

公开(公告)日：2007-05-22

申请号：US10850803

申请日：2004-05-21

Applicant: Steven C. Woo ,  Brian H. Tsang

Inventor： Steven C. Woo ,  Brian H. Tsang

IPC: G06F12/00 ,  G11C7/00

CPC classification number: G06F13/161 ,  G06F13/1631

Abstract: A memory system having multiple memory devices reduces average access latency by enabling different latencies for different regions of physical memory, providing an address map conducive to placing frequently accessed memory addresses into the lowest latency regions of physical memory; and assigning the frequently accessed memory addresses to the lowest latency regions of physical memory.

Abstract translation: 具有多个存储器件的存储器系统通过为不同的物理存储器区域启用不同的延迟来降低平均访问等待时间，从而提供有助于将频繁访问的存储器地址放置到物理存储器的最低延迟区域中的地址映射; 以及将经常访问的存储器地址分配给物理存储器的最低延迟区域。

公开(公告)号：US06523089B2

公开(公告)日：2003-02-18

申请号：US09907338

申请日：2001-07-16

Applicant: Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

Inventor： Ely K. Tsern ,  Ramprasad Satagopan ,  Richard M. Barth ,  Steven C. Woo

IPC: G06F1200

CPC classification number: G06F1/3275 ,  G06F1/3203 ,  G06F12/0215 ,  G06F2212/1028 ,  G11C11/4074 ,  Y02D10/13 ,  Y02D10/14

Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

公开(公告)号：US5386370A

公开(公告)日：1995-01-31

申请号：US124416

申请日：1993-09-21

Applicant: Steven C. Woo

Inventor： Steven C. Woo

IPC: G01S19/21 ,  G01S5/04 ,  G01S19/26 ,  G01S13/42

CPC classification number: G01S5/04

Abstract: First and second passive sensors (14,16), which may be mounted on different earth orbiting satellites, provide relative azimuth and elevation coordinates to sensed objects (A,B,C) such as hostile missiles. Minimum and maximum possible ranges to the objects (A,B,C) along lines-of-sight (18a,18b,18c) from the first sensor (14) are predetermined, and used to calculate "range lines" (24,26,28) which are coincident with the lines-of-sight (18a,18b,18c) and extend from the respective minimum to maximum ranges respectively. The range lines (24,26,28) are transformed into the field of view of the second sensor (16), and matched to the azimuth and elevation coordinates of the respective objects (A,B,C) using a basic feasible solution (greedy) or global optimization algorithm. The approximate points of intersection of lines-of-sight (20a,20b,20c) from the second sensor (16) to the objects (A,B,C) and matched range lines (24,26,28) are calculated, and transformed into coordinates relative to a reference point (10) such as the center of the earth (12). The calculations for the individual objects (A,B,C) may be performed simultaneously using parallel processors (44a,44b,44c) in a single instruction stream--multiple data stream (SIMD) or similar computing arrangement (40).

Abstract translation: 可以安装在不同的地球轨道卫星上的第一和第二无源传感器（14,16）为诸如敌对导弹的感测对象（A，B，C）提供相对方位和仰角坐标。 预定来自第一传感器（14）的沿视线（18a，18b，18c）的对象（A，B，C）的最小和最大可能范围，并用于计算“范围线”（24,26 ，28），其与视线（18a，18b，18c）重合，并分别从相应的最小值到最大范围。 将范围线（24,26,28）变换为第二传感器（16）的视场，并使用基本可行解（A，B，C）与各个对象（A，B，C）的方位角和仰角坐标相匹配 贪心）或全局优化算法。 计算从第二传感器（16）到对象（A，B，C）和匹配范围线（24,26,28）的视线（20a，20b，20c）的近似交点，并且 变换为相对于诸如地球（12）的中心的参考点（10）的坐标。 可以在单个指令流 - 多数据流（SIMD）或类似的计算装置（40）中使用并行处理器（44a，44b，44c）同时执行各个对象（A，B，C）的计算。

公开(公告)号：US09263103B2

公开(公告)日：2016-02-16

申请号：US12049928

申请日：2008-03-17

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G06F12/00 ,  G11C11/4076 ,  G06F3/06 ,  G06F5/06 ,  G06F1/08 ,  G11C7/10 ,  G06F13/16 ,  G06F12/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。 在该系统的变型中，存储器芯片上的相位检测器被配置为从存储器控制器接收包括时钟信号，标记信号和数据选通信号的信号，其中标记信号包括标记特定时钟的脉冲 在时钟信号周期。 在该变型中，相位检测器被配置为使用标记信号来在时钟信号中画出特定时钟周期，并且使用数据选通信号来捕获窗口化的时钟信号，从而产生返回到 内存控制器便于校准时序关系。

公开(公告)号：US20150255144A1

公开(公告)日：2015-09-10

申请号：US14698755

申请日：2015-04-28

Applicant: Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

Abstract translation: 描述了校准执行写操作所涉及的信号之间的时序关系的系统。 该系统包括耦合到一组存储器芯片的存储器控​​制器，其中每个存储器芯片包括相位检测器，该相位检测器被配置为在数据选通信号和存储器芯片之间从存储器控制器接收的时钟信号之间校准相位关系 一个写操作。 此外，存储器控制器被配置为执行一个或多个写入读取验证操作以校准数据选通信号和时钟信号之间的时钟周期关系，其中写入 - 读取验证操作涉及改变在 相对于时钟信号的数据选通信号乘以时钟周期的倍数。