公开(公告)号：US20050055481A1

公开(公告)日：2005-03-10

申请号：US10605140

申请日：2003-09-10

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F3/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/12 ,  G06F13/38 ,  G11C16/10

CPC分类号： G06F13/387 ,  G11C16/102

摘要： A flash-drive or flash-card reader connects to a personal computer (PC) through a serial link such as a Universal-Serial-Bus (USB), IEEE 1394, SATA, or IDE. A local CPU acts as the bus master of a CPU bus that connects to slave ports on a flash-memory controller, a serial engine, and a RAM buffer. A second bus in parallel to the CPU bus connects a second slave port on the RAM buffer to a master port on the flash-memory controller and to a master port on the serial engine. The flash-memory controller or the serial engine can use their master ports to transfer data to and from the RAM buffer using the second bus, allowing the CPU to retain control of the CPU bus. The second bus is a flash-serial buffer bus that improves data transfer rates. The flash-memory controller can prefetch into the RAM buffer.

摘要翻译： 闪存驱动器或闪存卡读卡器通过串行链路（例如通用串行总线（USB），IEEE 1394，SATA或IDE）连接到个人计算机（PC）。 本地CPU作为连接闪存控制器，串行引擎和RAM缓冲区的从站端口的CPU总线的总线主机。 与CPU总线并行的第二个总线将RAM缓冲器上的第二个从站端口连接到闪存控制器上的主站和串行引擎上的主站。 闪存控制器或串行引擎可以使用其主端口使用第二个总线将数据传输到RAM缓冲区，并允许CPU保留对CPU总线的控制。 第二个总线是提供数据传输速率的闪存串行缓冲区总线。 闪存控制器可以预取入RAM缓冲区。

公开(公告)号：US20050138288A1

公开(公告)日：2005-06-23

申请号：US10746935

申请日：2003-12-23

申请人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

发明人： Horng-Yee Chou ,  Ben Wei Chen ,  Sun-Teck See

IPC分类号： G06F12/00 ,  G06F13/40

CPC分类号： G06F13/409

摘要： A flash memory device for connecting to an ExpressCard™ host includes at least one flash memory module, an ExpressCard™ connector for connecting to the ExpressCard™ host, a first serial interface coupled to the ExpressCard™ connector, and a controller coupled to the first serial interface and the at least one flash memory module.

摘要翻译： 用于连接到ExpressCard TM主机的闪存设备包括至少一个闪存模块，用于连接到ExpressCard TM主机的ExpressCard TM连接器，耦合到ExpressCard TM连接器的第一串行接口， 以及耦合到所述第一串行接口和所述至少一个闪存模块的控制器。

公开(公告)号：US20050120146A1

公开(公告)日：2005-06-02

申请号：US10707277

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See ,  Charles Lee

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  G06F3/0679 ,  Y02D10/14

摘要： A Universal-Serial-Bus (USB) single-chip flash device contains a USB flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. USB packets from a host USB bus are read by a serial engine on the USB flash microcontroller. Various routines that execute on a CPU in the USB flash microcontroller are activated in response to commands in the USB packets. A flash-memory controller in the USB flash microcontroller transfers data from the serial engine to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

摘要翻译： 通用串行总线（USB）单芯片闪存器件包含一个USB闪存单片机和闪存大容量存储块，其中包含可寻址的闪存阵列，而不是随机寻址。 来自主机USB总线的USB数据包由USB闪存单片机上的串行引擎读取。 响应于USB数据包中的命令，激活在USB闪存单片机中的CPU上执行的各种例程。 USB闪存单片机中的闪存控制器将数据从串行引擎传输到闪存大容量存储块进行存储。 不是从耦合到CPU的内部ROM引导，引导加载程序由DMA从闪存大容量存储块的第一页传输到内部RAM。 在上电时，闪存将从第一页自动读取。 CPU然后从内部RAM执行引导加载程序来加载控制程序。

公开(公告)号：US20050114587A1

公开(公告)日：2005-05-26

申请号：US10707138

申请日：2003-11-22

申请人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

发明人： Horng-Yee Chou ,  Sun-Teck See ,  Tzu-Yih Chu

IPC分类号： G06F12/00 ,  G06F13/38

CPC分类号： G06F13/385

摘要： An ExpressCard contains flash memory. The ExpressCard has an ExpressCard connector that plugs into a host, such as a personal computer, digital camera, or personal digital assistant (PDA). A controller chip on the ExpressCard uses a pair of differential Universal-Serial-Bus (USB) data lines in the connector to communicate with the USB host, or can use PCI Express, Firewire, or other protocols. One or more flash-memory chips on the ExpressCard are controlled by a flash-memory controller in the controller chip. Two or more channels of a flash bus have a shared control bus but separate ready lines. The separate ready lines allow flash-memory chips in the two channels to finish operations at different times.

摘要翻译： ExpressCard包含闪存。 ExpressCard具有插入主机的ExpressCard连接器，如个人计算机，数码相机或个人数字助理（PDA）。 ExpressCard上的控制器芯片使用连接器中的一对差分通用串行总线（USB）数据线与USB主机进行通信，也可以使用PCI Express，Firewire或其他协议。 ExpressCard上的一个或多个闪存芯片由控制器芯片中的闪存控制器控制。 闪存总线的两个或更多个通道具有共享控制总线，但是分离的就绪线路。 单独的就绪线路允许两个通道中的闪存芯片在不同时间完成操作。

公开(公告)号：US07073010B2

公开(公告)日：2006-07-04

申请号：US10707276

申请日：2003-12-02

申请人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

发明人： Ben Wei Chen ,  Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F13/20

CPC分类号： G06F13/385

摘要： A dual-mode Universal-Serial-Bus (USB) switch can operate in a normal hub mode to buffer transactions from a host to multiple USB flash storage blocks that are USB endpoints. When operating in a single-endpoint mode, the dual-mode USB switch intercepts packets from the host and responds to the host as a single USB endpoint. The USB switch aggregates all downstream USB flash storage blocks and reports a single pool of memory to the host as a single virtual USB memory. Adjacent transactions can be overlapped by packet re-ordering. A token packet that starts a following transaction is re-ordered to be sent to the USB flash storage blocks before the data and handshake packets that end a first transaction, allowing the second transaction to begin accessing the flash memory earlier. Data can be mirrored or striped across several USB flash storage blocks and parity can be added for error recovery.

摘要翻译： 双模通用串行总线（USB）交换机可以在正常集线器模式下工作，以缓冲从主机到作为USB端点的多个USB闪存存储块的事务。 当以单端点模式运行时，双模式USB交换机将拦截主机的数据包，并作为单个USB端点作为主机响应。 USB转换器将所有下游USB闪存存储块聚合，并将单个存储器池作为单个虚拟USB存储器报告给主机。 相邻的事务可以通过重新排序重叠。 在数据和握手结束第一个事务的数据包之前，重新排序启动后续事务的令牌数据包，以便在第二个事务开始之前开始访问闪存。 数据可以跨几个USB闪存存储块进行镜像或条带化，并且可以添加奇偶校验以进行错误恢复。

公开(公告)号：US20050286284A1

公开(公告)日：2005-12-29

申请号：US10882005

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/00 ,  G11C11/34 ,  G11C16/02

CPC分类号： G11C16/02

摘要： Through the use of an allocation logic unit with a Flash controller, a single primary chip enable is de-multiplexed into a multiple secondary chip enables for multiple Flash memory dies or chips. In so doing, Flash storage device capacity is greatly expanded. In a first aspect, a memory package includes a plurality of memories; and an allocation logic unit coupled to the plurality of memories for receiving a single chip enable signal. The allocation logic unit de-multiplexes the single chip enable signal to a plurality of chip enable signals. Each of the plurality of chip enable signals access to one of the plurality of memories. In a second aspect, a printed circuit board (PCB) includes a Flash controller for providing at least one primary chip enable signal. The PCB also includes a plurality of Flash memory chips and at least one allocation logic unit coupled to at least a portion of the plurality of Flash memory chips and the Flash controller. The allocation logic unit receives the at least one chip enable signal and de-multiplexes the at least one chip enable signal to a plurality of secondary chip enable signals. Each of the plurality of chip enable signals controls access to one of the Flash memory chips.

摘要翻译： 通过使用具有闪存控制器的分配逻辑单元，单个主芯片使能被解复用到多个次级芯片中，使得能够用于多个闪存芯片或芯片。 这样做，Flash存储设备容量大大扩大。 在第一方面，一种存储器包括多个存储器; 以及耦合到所述多个存储器以用于接收单个芯片使能信号的分配逻辑单元。 分配逻辑单元将单芯片使能信号解复用到多个芯片使能信号。 多个芯片使能信号中的每一个访问多个存储器中的一个。 在第二方面，印刷电路板（PCB）包括用于提供至少一个主芯片使能信号的闪光控制器。 PCB还包括多个闪存芯片和耦合到多个闪存芯片和闪存控制器的至少一部分的至少一个分配逻辑单元。 所述分配逻辑单元接收所述至少一个芯片使能信号，并且将所述至少一个芯片使能信号解复用到多个次级芯片使能信号。 多个芯片使能信号中的每一个控制对闪存芯片之一的访问。

公开(公告)号：US20050285248A1

公开(公告)日：2005-12-29

申请号：US10881203

申请日：2004-06-29

申请人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

发明人： Sun-Teck See ,  Horng-Yee Chou ,  Charles Lee

IPC分类号： G11C5/04 ,  H01L23/02 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H05K1/18

CPC分类号： G11C5/04 ,  H01L23/49575 ,  H01L23/50 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.

摘要翻译： 描述了包括堆叠的多个存储器芯片的存储器封装和芯片架构。 在第一方面，一种存储器封装包括衬底和安装在衬底上的多个存储器管芯。 每个管芯都有独立的芯片使能。 在第二方面，芯片架构包括印刷电路板（PCB）。 PCB包括一个占位面积。 足迹包括至少一个无连接（NC）垫。 芯片架构包括安装在印刷电路板上的多个堆叠的存储器芯片。 多个堆叠存储器中的每一个具有芯片使能信号引脚，并且还具有至少一个NC引脚。 多个层叠的存储器芯片中的至少一个利用另一个堆叠的存储器芯片的NC引脚将芯片使能引脚路由到占用空间的至少一个NC焊盘。 因此，根据本发明的系统和方法通过（1）在单个存储器封装中提供多个管芯并且（2）通过在单个PCB封装中提供堆叠的存储器芯片来提供特定空间约束内的增加的存储器密度。 在这样做的同时，封装/ PCB将在相同的空间限制内在传统封装/ PCB上增加存储密度，并相应地扩展闪存存储设备的容量。

公开(公告)号：US20050251609A1

公开(公告)日：2005-11-10

申请号：US10839648

申请日：2004-05-04

申请人： Horng-Yee Chou ,  Sun-Teck See

发明人： Horng-Yee Chou ,  Sun-Teck See

IPC分类号： G06F3/00 ,  G06F13/40

CPC分类号： G06F13/4081 ,  G06F2213/0026 ,  G06F2213/0042

摘要： A peripheral device coupleable to an ExpressCard™ interface of a host system includes an ExpressCard™ portion and a second portion coupleable to the ExpressCard™ portion. Functionality of the peripheral device is partitioned between the ExpressCard™ portion and the second portion.

摘要翻译： 可耦合到主机系统的ExpressCard TM接口的外围设备包括ExpressCard TM部分和可连接到ExpressCard TM部分的第二部分。 外围设备的功能在ExpressCard TM部分和第二部分之间分配。

公开(公告)号：US07673080B1

公开(公告)日：2010-03-02

申请号：US10917576

申请日：2004-08-13

申请人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

发明人： I-Kang Yu ,  Horng-Yee Chou ,  Szu-Kuang Chou ,  Charles C. Lee

IPC分类号： G06F13/12 ,  G06F13/00

CPC分类号： G06F13/387 ,  G06F13/385 ,  G06K19/07732 ,  G06K19/07733 ,  Y02D10/14 ,  Y02D10/151

摘要： A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultiMediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

摘要翻译： 闪存卡包括差分数据路径，其使得能够使用差分信号执行闪存卡与主机设备之间的通信。 差分数据路径可以在差分信号和控制对闪存卡的存储器阵列的读/写操作的卡特定信号之间进行转换。 特定于卡的信号可以是标准的多媒体卡，安全数字卡，记忆棒或CompactFlash卡信号。 提供差分数据传输能力的主机设备可以包括类似的差分数据路径。 通过使用差分数据传输而不是传统的时钟数据传输，闪存卡和主机设备之间的总体数据带宽可以显着增加，同时降低功耗和引脚要求。

公开(公告)号：US07657692B2

公开(公告)日：2010-02-02

申请号：US11926636

申请日：2007-10-29

申请人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

发明人： Charles C. Lee ,  David Q. Chow ,  Abraham C. Ma ,  Frank Yu ,  Ming-Shiang Shen ,  Horng-Yee Chou

IPC分类号： G06F13/00

CPC分类号： G06F13/28 ,  G06F12/1416 ,  G06F21/32 ,  G06F21/78 ,  G06K9/00087 ,  G06K19/07 ,  G06K19/07354 ,  G07C9/00087

摘要： An extended universal-serial bus (EUSB) bridge to a host computer can have peripheral component interconnect express (PCIE) protocol layers on one side of the bridge, and EUSB layers on the other side of the bridge, with a high-level bridging converter module connecting the upper layers. The PCIE physical, data-link, and transport layers may be eliminated by integrating the bridge with an I/O controller. PCIE requests and data payloads are directly sent to the bridge, rather than low-level PCIE physical signals. The PCIE data payloads are converted to EUSB data payloads by a high-level direct bridging converter module. Then the EUSB data payloads are passed down to an EUSB transaction layer, an EUSB data-link layer, and an EUSB physical layer which drives and senses physical electrical signals on both differential pairs of the EUSB bus.

摘要翻译： 到主机的扩展通用串行总线（EUSB）桥可以在桥的一侧具有外围组件互连快速（PCIE）协议层，并且在桥的另一侧可以具有高级桥接转换器 模块连接上层。 可以通过将桥与I / O控制器集成来消除PCIE物理，数据链路和传输层。 PCIE请求和数据有效载荷直接发送到桥，而不是低级PCIE物理信号。 PCIE数据有效载荷通过高级直接桥接转换器模块转换为EUSB数据有效载荷。 然后，EUSB数据有效载荷被传递到EUSB事务层，EUSB数据链路层和EUSB物理层，其在EUSB总线的两个差分对上驱动和感测物理电信号。