公开(公告)号：US07094707B1

公开(公告)日：2006-08-22

申请号：US10142963

申请日：2002-05-13

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L23/58

CPC classification number: H01L21/28202 ,  H01L21/28035 ,  H01L29/518

Abstract: A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.

Abstract translation: 提供了一种通过在热壁中的一氧化氮（NO）气体退火预形成的氧化物层来对栅极氧化物层进行氮化的方法。 氮化处理可以快速进行（即，在30秒至2分钟的氮化时间），同时提供可接受的氮化水平（即高达6原子％）和所需的氮/深度分布。 氮化栅氧化层可以在氮化步骤后的第二氧化步骤中任选地再氧化。 然后可以在氮化栅极氧化物层的顶部上或在再氧化和氮化的栅极氧化物层的顶部上沉积栅极电极层（例如，硼掺杂的多晶硅）。

公开(公告)号：US06943126B1

公开(公告)日：2005-09-13

申请号：US10314381

申请日：2002-12-06

Applicant: Sundar Narayanan ,  Krishnaswamy Ramkumar

Inventor： Sundar Narayanan ,  Krishnaswamy Ramkumar

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/0217 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/28176 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32139 ,  H01L21/76834 ,  H01L29/518

Abstract: A method of forming a semiconductor structure comprises forming an etch-stop layer comprising nitride, on a stack. The stack is on a semiconductor substrate, and the stack comprises (i) a gate layer. The forming is by CVD with a gas comprising a first compound which is SixL2x, and a second compound comprising nitrogen and deuterium, L is an amino group, and X is 1 or 2.

Abstract translation: 形成半导体结构的方法包括在叠层上形成包含氮化物的蚀刻停止层。 堆叠在半导体衬底上，堆叠包括（i）栅极层。 通过CVD形成是用包含第二化合物的气体，该第一化合物是Si x L 2 x X 2，以及包含氮和氘的第二化合物，L是氨基，X是 是1或2。

公开(公告)号：US06794269B1

公开(公告)日：2004-09-21

申请号：US10324989

申请日：2002-12-20

Applicant: Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

Inventor： Prabhuram Gopalan ,  Biju Parameshwaran ,  Krishnaswamy Ramkumar ,  Hanna Bamnolker ,  Sundar Narayanan

IPC: H01L2176

CPC classification number: H01L21/763 ,  H01L21/76202

Abstract: A method is provided which includes forming a deep isolation structure within a semiconductor topography. In some cases, the method may include forming a first isolation structure within a semiconductor layer and etching an opening within the isolation structure to expose the semiconductor layer. In addition, the method may include etching the semiconductor layer to form a trench extending through the isolation structure and at least part of the semiconductor layer. In some cases, the method may include removing part of a first fill layer deposited within the trench such that an upper surface of the fill layer is below an upper portion of the trench. In such an embodiment, the vacant portion of the trench may be filled with a second fill layer. In yet other embodiments, the method may include planarizing the first fill layer within the trench and subsequently oxidizing an upper portion of the fill layer.

Abstract translation: 提供了一种方法，其包括在半导体形貌内形成深度隔离结构。 在一些情况下，该方法可以包括在半导体层内形成第一隔离结构并蚀刻隔离结构内的开口以暴露半导体层。 此外，该方法可以包括蚀刻半导体层以形成延伸穿过隔离结构和半导体层的至少一部分的沟槽。 在一些情况下，该方法可以包括去除沉积在沟槽内的第一填充层的部分，使得填充层的上表面在沟槽的上部下方。 在这样的实施例中，沟槽的空缺部分可以填充第二填充层。 在其他实施例中，该方法可以包括平坦化沟槽内的第一填充层，随后氧化填充层的上部。

公开(公告)号：US08710578B2

公开(公告)日：2014-04-29

申请号：US13431069

申请日：2012-03-27

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/785 ,  H01L29/7926

Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

Abstract translation: 描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。 通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离 从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。 还公开了其他实施例。

公开(公告)号：US20130178030A1

公开(公告)日：2013-07-11

申请号：US13434347

申请日：2012-03-29

Applicant: Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

Inventor： Krishnaswamy Ramkumar ,  Bo Jin ,  Fredrick Jenne

IPC: H01L21/336

CPC classification number: B82Y10/00 ,  H01L21/28282 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域之上形成MOS器件的焊盘电介质层; 从半导体材料的薄膜形成存储器件的沟道，该半导体材料的薄膜覆盖在衬底的第二区域上方的表面，所述通道连接存储器件的源极和漏极; 形成覆盖在第二区域上方的通道上的图案化电介质堆叠，所述图案化电介质叠层包括隧道层，电荷俘获层和牺牲顶层; 同时从衬底的第二区域去除牺牲顶层，以及从衬底的第一区域去除焊盘介电层; 并且同时在衬底的第一区域上方形成栅极电介质层，并且在电荷俘获层上方形成阻挡电介质层。

公开(公告)号：US20130175504A1

公开(公告)日：2013-07-11

申请号：US13436872

申请日：2012-03-31

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/775

CPC classification number: H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

Abstract translation: 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。

公开(公告)号：US08143129B2

公开(公告)日：2012-03-27

申请号：US12185747

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

Inventor： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US07898852B1

公开(公告)日：2011-03-01

申请号：US12005803

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Peter Voss

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Peter Voss

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C11/56 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

Abstract: Methods and apparatus for programming and sensing a bi-nitride layer trapped-charge memory device in one of a first and second programmed states or one of a first and second erased states, where the first and second programmed states correspond to first and second uniform trapped charge distributions of a first charge type and the first and second erased states correspond to first and second uniform trapped charge distributions of a second charge type.

Abstract translation: 用于以第一和第二编程状态或第一和第二擦除状态中的一种编程和感测二氮化物层捕获电荷存储器件的方法和装置，其中第一和第二编程状态对应于第一和第二均匀捕获 第一充电类型和第一和第二擦除状态的电荷分布对应于第二充电类型的第一和第二均匀俘获电荷分布。

公开(公告)号：US07867918B1

公开(公告)日：2011-01-11

申请号：US12046073

申请日：2008-03-11

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.

Abstract translation: 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可用于形成半导体器件，其包括具有小于约20埃的电等效氧化物栅极薄膜厚度的氧化物 - 氮化物栅极电介质。

公开(公告)号：US07670963B2

公开(公告)日：2010-03-02

申请号：US11904513

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/469

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833 ,  Y10S438/954

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。 然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。 然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。