公开(公告)号：US10062419B2

公开(公告)日：2018-08-28

申请号：US15830599

申请日：2017-12-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

发明人： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Wei-Cheng Wu ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： G11C11/00 ,  H01L27/088 ,  G11C7/02 ,  G11C11/412 ,  G11C11/419

CPC分类号： G11C7/02 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1104

摘要： In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.

公开(公告)号：US09666253B2

公开(公告)日：2017-05-30

申请号：US14924069

申请日：2015-10-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jonathan Tsung-Yung Chang ,  Chiting Cheng ,  Cheng Hung Lee ,  Hung-Jen Liao ,  Michael Clinton

IPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  G11C8/10 ,  G11C8/06 ,  G11C8/08

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C5/147 ,  G11C7/06 ,  G11C7/065 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C8/08 ,  G11C8/10 ,  G11C11/417 ,  G11C11/418

摘要： A dual rail memory operable at a first voltage and a second voltage, the dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal; and a control circuit configured to generate control signals to the memory array, the word line driver circuit and the data path; wherein the data path and the control circuit are configured to operate at both the first and second voltages. Associated memory macro and method are also disclosed.

公开(公告)号：US09589885B2

公开(公告)日：2017-03-07

申请号：US14835788

申请日：2015-08-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hung-Jen Liao ,  Jung-Hsuan Chen ,  Chien Chi Tien ,  Ching-Wei Wu ,  Jui-Che Tsai ,  Hong-Chen Cheng ,  Chung-Hsing Wang

IPC分类号： H01L23/00 ,  H01L23/50 ,  H01L27/11 ,  H01L23/532 ,  H01L27/02 ,  H01L23/528 ,  H01L23/498 ,  H01L23/522

CPC分类号： H01L23/50 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L27/0203 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) memory device includes a first conductive layer. The IC memory device also includes a second conductive layer over the first conductive layer. The IC memory device further includes a first-type pin box electrically coupled with the first conductive layer. The IC memory device additionally includes a second-type pin box, different from the first-type pin box, electrically coupled with the second conductive layer.

摘要翻译： 集成电路（IC）存储器件包括第一导电层。 IC存储器件还包括在第一导电层上的第二导电层。 IC存储器件还包括与第一导电层电耦合的第一型引脚盒。 IC存储器件还包括与第一类型引脚盒不同的第二型引脚盒，与第二导电层电耦合。

公开(公告)号：US09425095B2

公开(公告)日：2016-08-23

申请号：US14720824

申请日：2015-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： You-Cheng Xiao ,  Yen-Huei Chen ,  Jung-Hsuan Chen ,  Shao-Yu Chou ,  Li-Chun Tien ,  Hung-Jen Liao

IPC分类号： H01L21/768 ,  H01L23/528 ,  H01L23/482 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L21/76879 ,  H01L21/768 ,  H01L21/76832 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.

公开(公告)号：US09418729B2

公开(公告)日：2016-08-16

申请号：US15007894

申请日：2016-01-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hidehiro Fujiwara ,  Kao-Cheng Lin ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC分类号： G11C7/10 ,  G11C11/417 ,  G11C5/02 ,  G11C5/06

CPC分类号： G11C11/419 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/14 ,  G11C8/16 ,  G11C11/417 ,  H01L23/535 ,  H01L27/1104

摘要： A circuit includes a first data line, a second data line, a reference node, and a memory cell. The memory cell includes a data node, a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor are connected in series between the first data line and the reference node. The first transistor is configured to be turned off when the gate of the first transistor has a voltage level corresponding to the first logical value. The third transistor is between the data node and the second data line. The third transistor is configured to be turned off when a gate of the third transistor has a voltage level corresponding to a second logical value different from the first logical value.

摘要翻译： 电路包括第一数据线，第二数据线，参考节点和存储器单元。 存储单元包括数据节点，第一晶体管，第二晶体管和第三晶体管。 第一晶体管和第二晶体管串联连接在第一数据线和参考节点之间。 当第一晶体管的栅极具有与第一逻辑值对应的电压电平时，第一晶体管被配置为截止。 第三晶体管位于数据节点和第二数据线之间。 当第三晶体管的栅极具有与不同于第一逻辑值的第二逻辑值相对应的电压电平时，第三晶体管被配置为截止。

公开(公告)号：US09129956B2

公开(公告)日：2015-09-08

申请号：US14102623

申请日：2013-12-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hung-Jen Liao ,  Jung-Hsuan Chen ,  Chien Chi Tien ,  Ching-Wei Wu ,  Jui-Che Tsai ,  Hong-Chen Cheng ,  Chung-Hsing Wang

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L27/11 ,  H01L23/532 ,  H01L27/02 ,  H01L23/528

CPC分类号： H01L23/50 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53204 ,  H01L27/0203 ,  H01L27/11 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) memory device that includes a first conductive layer, a second conductive layer electrically coupled to the first conductive layer, the second conductive layer formed over the first conductive layer, a third conductive layer separated from the second conductive layer, the third conductive layer formed over the second conductive layer, a fourth conductive layer electrically coupled to the third conductive layer, the fourth conductive layer formed over the third conductive layer, a 2P2E pin box formed in and electrically coupled to the first conductive layer or the second conductive layer and a 1P1E pin box formed in and electrically coupled to the third conductive layer or the fourth conductive layer.

摘要翻译： 一种集成电路（IC）存储器件，其包括第一导电层，电耦合到第一导电层的第二导电层，形成在第一导电层上的第二导电层，与第二导电层分离的第三导电层， 形成在所述第二导电层上的第三导电层，电耦合到所述第三导电层的第四导电层，形成在所述第三导电层上的所述第四导电层，形成在所述第一导电层中或与所述第二导电层电连接的第二导电层， 导电层和形成在第三导电层或第四导电层中并电耦合到第三导电层的1P1E引脚盒。

公开(公告)号：US12119052B2

公开(公告)日：2024-10-15

申请号：US18362736

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

公开(公告)号：US12072750B2

公开(公告)日：2024-08-27

申请号：US18337449

申请日：2023-06-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Chen Kuo ,  Yangsyu Lin ,  Yu-Hao Hsu ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC分类号： G06F1/32 ,  G06F1/3206 ,  G06F1/3234

CPC分类号： G06F1/3206 ,  G06F1/3275

摘要： A circuit includes a power detector and a logic circuit. The power detector is configured to output a first power management signal according to a first power supply signal from a first power supply and a status signal. The circuit is configured to operate in different modes in response to the status signal. The logic circuit is configured to output a second power management signal, according to the first power management signal and the status signal.

公开(公告)号：US11910587B2

公开(公告)日：2024-02-20

申请号：US17410860

申请日：2021-08-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hidehiro Fujiwara ,  Yi-Hsin Nien ,  Hung-Jen Liao

IPC分类号： H10B10/00

CPC分类号： H10B10/18 ,  H10B10/12

摘要： An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

公开(公告)号：US11763882B2

公开(公告)日：2023-09-19

申请号：US17814700

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Mahmut Sinangil ,  Yen-Huei Chen ,  Yen-Ting Lin ,  Hung-Jen Liao ,  Jonathan Tsung-Yung Chang

IPC分类号： G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.