公开(公告)号：US11011238B2

公开(公告)日：2021-05-18

申请号：US16204268

申请日：2018-11-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Manish Arora ,  Hung-Jen Liao ,  Yen-Huei Chen ,  Nikhil Puri ,  Yu-Hao Hsu

IPC: G11C16/06 ,  G11C16/24 ,  H01L27/11551 ,  G11C7/12 ,  G11C16/04 ,  G11C11/00 ,  H01L27/11524

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, a first input node configured to receive a first data signal, a second input node configured to receive a second data signal, a third input node configured to receive a control signal, and an output node. The write line circuit is configured to, responsive to the first data signal, the second data signal, and the control signal, either output one of the power supply voltage level or the reference voltage level on the output node, or float the output node.

公开(公告)号：US10354952B2

公开(公告)日：2019-07-16

申请号：US14528337

申请日：2014-10-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Li-Wen Wang ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  G06F17/50 ,  H01L27/02

Abstract: A memory cell comprises a first word line in a first layer on a first level. The memory cell also comprises a second word line having a first portion in the first layer and a second portion in a second layer. The second layer is on a second level different from the first level. The memory cell further comprises a first via layer coupling the first portion of the second word line with the second portion of the second word line.

公开(公告)号：US10170487B2

公开(公告)日：2019-01-01

申请号：US15333439

申请日：2016-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Hsien Huang ,  Hong-Chen Cheng ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: H01L27/112 ,  H01L23/522 ,  G11C7/18 ,  H01L21/768 ,  H01L23/528 ,  H01L27/06

Abstract: A three-dimensional integrated circuit includes a first transistor, a word line, a first via, a second transistor, and a second via. The first transistor is on a first level and the second transistor is on a second level. The second level is different from the first level. The word line and the first via are coupled to the first transistor. The second via is coupled between the first transistor and the second transistor.

公开(公告)号：US20180090183A1

公开(公告)日：2018-03-29

申请号：US15830599

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Wei-Cheng Wu ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C7/02 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C7/02 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1104

Abstract: In accordance with some embodiments of the present disclosure, a circuit structure is provided. The circuit structure comprises a first transistor, a second transistor, a storage node and a word-line. Each of the two transistors comprises a gate, a source and a drain. The storage node is connected to the gate of the first transistor. The word-line is connected to the gate of the second transistor. The first and second transistors are serially connected. The first and second threshold voltages are respectively associated with the first and second transistors, and the first threshold voltage is lower than the second threshold voltage.

公开(公告)号：US09704565B2

公开(公告)日：2017-07-11

申请号：US15012970

申请日：2016-02-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Wei Min Chan ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Ping-Wei Wang

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/4063 ,  G11C11/409 ,  G11C11/412

Abstract: A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.

公开(公告)号：US09607683B1

公开(公告)日：2017-03-28

申请号：US14969632

申请日：2015-12-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hidehiro Fujiwara ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: G11C11/00 ,  G11C11/417 ,  G11C11/412 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C7/227 ,  G11C8/08 ,  G11C11/418

Abstract: In some embodiments, a semiconductor device includes an SRAM cell, an emulator and a suppressing device. The SRAM cell, enabled by a word line, includes a first inverter formed by a first PMOS transistor and a first NMOS transistor and stores a first data at an output of the first inverter. The emulator is configured to emulate the first inverter operating in a condition that the PMOS transistor is weaker than the first NMOS transistor in driving strength. The suppressing device is configured to, in response to a voltage at an output of the emulator, selectively suppress a voltage level of the word line.

公开(公告)号：US09484350B2

公开(公告)日：2016-11-01

申请号：US14039481

申请日：2013-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Hsien Huang ,  Hong-Chen Cheng ,  Cheng-Hung Lee ,  Hung-Jen Liao

IPC: H01L29/76 ,  H01L27/112 ,  G11C7/18 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/1128 ,  G11C7/18 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device.

Abstract translation: 三维半导体器件包括第一存储器件，第二存储器件和通孔。 通孔将第一存储器件连接到第二存储器件。

公开(公告)号：US08665654B2

公开(公告)日：2014-03-04

申请号：US13924176

申请日：2013-06-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hong-Chen Cheng ,  Ming-Yi Lee ,  Kuo-Hua Pan ,  Jung-Hsuan Chen ,  Li-Chun Tien ,  Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C7/10

CPC classification number: G11C5/06 ,  G11C5/147 ,  G11C5/148 ,  G11C11/417

Abstract: A column of a memory includes a first edge cell and at least one memory cell. The first edge cell is located at a first edge of the column and includes a first edge cell reference node and a second edge cell reference node. Each of the at least one memory cells includes a first memory reference node. The first edge cell reference node is coupled to respective first memory reference nodes of the at least one memory cell. The second edge cell reference node serves as second memory reference nodes of the at least one memory cell. Front-end layers of the first edge cell are the same as front-end layers of a memory cell of the at least one memory cell.

Abstract translation: 存储器的列包括第一边缘单元和至少一个存储单元。 第一边缘单元位于列的第一边缘，并且包括第一边缘单元参考节点和第二边缘单元参考节点。 所述至少一个存储器单元中的每一个包括第一存储器参考节点。 第一边缘单元参考节点耦合到至少一个存储器单元的相应的第一存储器参考节点。 第二边缘单元参考节点用作至少一个存储单元的第二存储器参考节点。 第一边缘单元的前端层与至少一个存储单元的存储单元的前端层相同。

公开(公告)号：US12136460B2

公开(公告)日：2024-11-05

申请号：US18362549

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Manish Arora ,  Yen-Huei Chen ,  Hung-Jen Liao ,  Nikhil Puri ,  Yu-Hao Hsu

IPC: G11C16/24 ,  G11C7/12 ,  G11C11/00 ,  G11C16/04 ,  H10B41/20 ,  H10B41/35

Abstract: A memory circuit includes first and second memory segments coupled to first and second write lines, and first and second write line circuits coupled to the first and second write lines and configured to receive first and second data signals. The first and second data signals have complementary low and high logical states during a write operation to the first or second memory segment, and each of the first and second data signals has the low logical state during a masked write operation to the first or second memory segment. The first and second write line circuits output, to the first and second write lines, first and second write line signals responsive to the first and second data signals during the write operation and float the first and second data lines during the masked write operation.

公开(公告)号：US12029023B2

公开(公告)日：2024-07-02

申请号：US18304301

申请日：2023-04-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hidehiro Fujiwara ,  Chih-Yu Lin ,  Hsien-Yu Pan ,  Yasutoshi Okuno ,  Yen-Huei Chen ,  Hung-Jen Liao

IPC: H10B10/00 ,  G06F30/392 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H10B10/12 ,  G06F30/392 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull down transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact. The first metal contact layout pattern overlaps the cell boundary of the memory circuit and the first active region layout pattern. The first metal contact electrically coupled to a source of the first pull down transistor. The memory circuit being a four transistor (4T) memory cell including a first and second pass gate transistor, and a first and second pull down transistor.