公开(公告)号：US07112264B2

公开(公告)日：2006-09-26

申请号：US10606956

申请日：2003-06-27

申请人： Hidetoshi Tsuzuki ,  Noboru Toyama ,  Yasuyoshi Takai ,  Ryo Hayashi ,  Yuichi Sonoda ,  Masumitsu Iwata ,  Yusuke Miyamoto

发明人： Hidetoshi Tsuzuki ,  Noboru Toyama ,  Yasuyoshi Takai ,  Ryo Hayashi ,  Yuichi Sonoda ,  Masumitsu Iwata ,  Yusuke Miyamoto

IPC分类号： C25D5/02 ,  C25D7/06 ,  C25D17/00

CPC分类号： C25D7/0671 ,  C25D5/028

摘要： A plating apparatus includes a plating vessel for holding a plating bath containing at least metal ions, a conveying device for conveying a long conductive substrate and immersing the long conductive substrate in the plating bath, a facing electrode disposed in the plating bath so as to face one surface of the conductive substrate, a voltage application device for performing plating on the one surface of the conductive substrate by applying a voltage between the conductive substrate and the facing electrode, and a film-deposition suppression device fixedly disposed in the plating vessel so that at least a portion of the film-deposition suppression means is close to shorter-direction edges of the conductive substrate. At least a portion of the film-deposition suppression device close to the shorter-direction edges of the conductive substrate is conductive. By holding the conductive portion of the film-deposition suppression device and the conductive substrate at substantially the same potential, film deposition on the other surface of the conductive substrate is suppressed.

摘要翻译： 电镀装置包括用于保持至少含有金属离子的电镀槽的电镀容器，用于输送长导电性基板并将长导电性基材浸渍在电镀槽中的输送装置，设置在镀浴中的面对电极， 导电基板的一个表面，通过在导电基板和对置电极之间施加电压在导电基板的一个表面上进行电镀的电压施加装置和固定地设置在电镀槽中的成膜抑制装置，使得 至少一部分成膜抑制装置接近导电基板的短边缘。 靠近导电基板的短边缘的薄膜沉积抑制装置的至少一部分是导电的。 通过将成膜抑制装置的导电部分和导电基板保持在基本相同的电位，抑制导电基板的另一个表面上的成膜。

公开(公告)号：US20080096291A1

公开(公告)日：2008-04-24

申请号：US11871534

申请日：2007-10-12

申请人： Yasuyoshi Takai ,  Tadashi Sawayama ,  Koichiro Moriyama

发明人： Yasuyoshi Takai ,  Tadashi Sawayama ,  Koichiro Moriyama

IPC分类号： H01L21/00

CPC分类号： H01L21/67253 ,  C23C16/24 ,  C23C16/4401 ,  C23C16/509 ,  C23C16/545 ,  H01L31/1824 ,  Y02E10/545 ,  Y02P70/521

摘要： A method for forming a semiconductor device including a semiconductor layer, formed of a silicon-based deposited film containing crystals by plasma-enhanced CVD, includes the steps of applying a bias voltage between a high-frequency electrode and a substrate with the high-frequency electrode being negative when the semiconductor layer is formed; detecting sparks occurring on the high-frequency electrode or the substrate; and controlling at least one condition, selected from the group consisting of high-frequency power, bias voltage, bias current, pressure, gas flow rate, and interelectrode distance, based on the results of the detection so that the number of sparks with durations of 100 ms or more is 1 or less sparks per minute.

摘要翻译： 一种用于形成半导体器件的方法，包括通过等离子体增强CVD由含有晶体的硅基沉积膜形成的半导体层，包括以下步骤：在高频电极和衬底之间施加高频 当形成半导体层时，电极为负极; 检测在高频电极或基板上发生的火花; 并且基于检测结果控制从由高频功率，偏置电压，偏置电流，压力，气体流量和电极间距离组成的组中选择的至少一个条件，使得具有持续时间的火花的数量 100 ms以上是每分钟1次以下的火花。

公开(公告)号：US07534628B2

公开(公告)日：2009-05-19

申请号：US11871534

申请日：2007-10-12

申请人： Yasuyoshi Takai ,  Tadashi Sawayama ,  Koichiro Moriyama

发明人： Yasuyoshi Takai ,  Tadashi Sawayama ,  Koichiro Moriyama

IPC分类号： H01L21/00 ,  H01L21/324 ,  C23C14/00

CPC分类号： H01L21/67253 ,  C23C16/24 ,  C23C16/4401 ,  C23C16/509 ,  C23C16/545 ,  H01L31/1824 ,  Y02E10/545 ,  Y02P70/521

摘要： A method for forming a semiconductor device including a semiconductor layer, formed of a silicon-based deposited film containing crystals by plasma-enhanced CVD, includes the steps of applying a bias voltage between a high-frequency electrode and a substrate with the high-frequency electrode being negative when the semiconductor layer is formed; detecting sparks occurring on the high-frequency electrode or the substrate; and controlling at least one condition, selected from the group consisting of high-frequency power, bias voltage, bias current, pressure, gas flow rate, and interelectrode distance, based on the results of the detection so that the number of sparks with durations of 100 ms or more is 1 or less sparks per minute.

摘要翻译： 一种用于形成半导体器件的方法，包括通过等离子体增强CVD由含有晶体的硅基沉积膜形成的半导体层，包括以下步骤：在高频电极和衬底之间施加高频 当形成半导体层时，电极为负极; 检测在高频电极或基板上发生的火花; 并且基于检测结果控制从由高频功率，偏置电压，偏置电流，压力，气体流量和电极间距离组成的组中选择的至少一个条件，使得具有持续时间的火花的数量 100 ms以上是每分钟1次以下的火花。

公开(公告)号：US06223684B1

公开(公告)日：2001-05-01

申请号：US09110124

申请日：1998-07-06

申请人： Yasushi Fujioka ,  Masahiro Kanai ,  Yasuyoshi Takai

发明人： Yasushi Fujioka ,  Masahiro Kanai ,  Yasuyoshi Takai

IPC分类号： C23C1600

CPC分类号： H01J37/32623 ,  C23C16/4401 ,  C23C16/4412 ,  C23C16/50 ,  Y10S156/916

摘要： A film deposition apparatus includes a vacuum chamber, a gas supplier, a gas exhauster, and a discharging means, the film deposition apparatus forming a deposited film on a substrate provided in the vacuum chamber by a plasma enhanced CVD process, wherein at least one louver is provided at the interior and/or vicinity of the plasma discharging space in the vacuum chamber.

摘要翻译： 成膜装置包括真空室，气体供给器，排气装置和排出装置，该成膜装置通过等离子体增强CVD工艺在设置在真空室中的基板上形成沉积膜，其中至少一个百叶窗 设置在真空室中的等离子体放电空间的内部和/或附近。

公开(公告)号：US09166502B2

公开(公告)日：2015-10-20

申请号：US13587751

申请日：2012-08-16

申请人： Yoshihiro Hasegawa ,  Yasuyoshi Takai

发明人： Yoshihiro Hasegawa ,  Yasuyoshi Takai

IPC分类号： H04R31/00 ,  H02N1/00 ,  H01G5/16

CPC分类号： B06B1/0292 ,  H01G5/16 ,  H02N1/006 ,  Y10T29/43

摘要： The present invention provides a technology for decreasing a dispersion of the performance among electromechanical transducers each having through wiring. A method for manufacturing an electromechanical transducer includes: obtaining a structure in which an insulative portion having a through hole therein is bonded onto an electroconductive substrate; filling the through hole with an electroconductive material to form a through wiring which is electrically connected with the electroconductive substrate; and using the electroconductive substrate as a first electrode, forming a plurality of vibrating membrane portions including a second electrode, which opposes to the first electrode through a plurality of gaps, on an opposite side of the first electrode to the side having the insulative portion, to thereby forming a plurality of cells.

摘要翻译： 本发明提供了一种用于减小每个具有通过布线的机电换能器之间的性能分散的技术。 制造机电换能器的方法包括：获得其中具有通孔的绝缘部分结合到导电基底上的结构; 用导电材料填充通孔以形成与导电基板电连接的贯通布线; 并且使用所述导电性基板作为第一电极，在所述第一电极的与所述绝缘部的一侧相反的一侧形成多个振动膜部，所述多个振动膜部包括与所述第一电极相对的多个间隙的第二电极， 从而形成多个单元。

公开(公告)号：US20110092016A1

公开(公告)日：2011-04-21

申请号：US12865032

申请日：2009-03-02

申请人： Masato Ofuji ,  Katsumi Abe ,  Hisae Shimizu ,  Ryo Hayashi ,  Masafumi Sano ,  Hideya Kumomi ,  Yasuyoshi Takai ,  Takehiko Kawasaki ,  Norio Kaneko

发明人： Masato Ofuji ,  Katsumi Abe ,  Hisae Shimizu ,  Ryo Hayashi ,  Masafumi Sano ,  Hideya Kumomi ,  Yasuyoshi Takai ,  Takehiko Kawasaki ,  Norio Kaneko

IPC分类号： H01L21/26 ,  H01L21/34

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H01L29/78633

摘要： In a method of treating a semiconductor element which at least includes a semiconductor, a threshold voltage of the semiconductor element is changed by irradiating the semiconductor with light with a wavelength longer than an absorption edge wavelength of the semiconductor. The areal density of in-gap states in the semiconductor is 1013 cm−2eV−1 or less. The band gap may be 2 eV or greater. The semiconductor may include at least one selected from the group consisting of In, Ga, Zn and Sn. The semiconductor may be one selected from the group consisting of amorphous In—Ga—Zn—O (IGZO), amorphous In—Zn—O (IZO) and amorphous Zn—Sn—O (ZTO). The light irradiation may induce the threshold voltage shift in the semiconductor element, the shift being of the opposite sign to the threshold voltage shift caused by manufacturing process history, time-dependent change, electrical stress or thermal stress.

摘要翻译： 在处理至少包括半导体的半导体元件的方法中，通过用比半导体的吸收边缘波长更长的光照射半导体来改变半导体元件的阈值电压。 半导体中间隙状态的面密度为1013cm-2eV-1或更小。 带隙可以是2eV或更大。 半导体可以包括选自In，Ga，Zn和Sn中的至少一种。 半导体可以是选自由无定形In-Ga-Zn-O（IGZO），非晶In-Zn-O（IZO）和无定形Zn-Sn-O（ZTO）组成的组中的一种。 光照射可以引起半导体元件中的阈值电压偏移，该偏移与由制造工艺历史，时间依赖变化，电应力或热应力引起的阈值电压偏移相反。

公开(公告)号：US06930025B2

公开(公告)日：2005-08-16

申请号：US10059168

申请日：2002-01-31

申请人： Akiya Nakayama ,  Hiroshi Echizen ,  Yasuyoshi Takai ,  Naoto Okada ,  Shigeo Kiso

发明人： Akiya Nakayama ,  Hiroshi Echizen ,  Yasuyoshi Takai ,  Naoto Okada ,  Shigeo Kiso

IPC分类号： C23C14/02 ,  H01L31/0224 ,  H01L31/052 ,  H01L31/18 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L31/1884 ,  C23C14/024 ,  H01L31/022466 ,  H01L31/022483 ,  H01L31/056 ,  Y02E10/52

摘要： In a process for forming on a substrate a transparent conductive film having crystallizability, the process comprises a first step of forming a film at a first film formation rate and a second step of forming a film at a second film formation rate, and the relationship between film formation rates in the respective steps satisfies: 2≦(second film formation rate)/(first film formation rate)≦100; which provides a process for producing a transparent conductive film by a deposition process advantageous for cost reduction, which can form in a short time a transparent conductive film having an uneven surface profile with a high light-confining effect, and can bring about an improvement in photovoltaic performance and enjoy a high mass productivity when applied to the formation of multi-layer structure of photovoltaic devices.

摘要翻译： 在基板上形成具有结晶性的透明导电膜的方法中，该方法包括以第一成膜速度形成薄膜的第一步骤和以第二薄膜形成速率形成薄膜的第二步骤 各步骤中的成膜速度满足：<？in-line-formula description =“In-line formula”end =“lead”？> 2 <=（第二成膜速率）/（第一成膜速率）<= 100 ; <？in-line-formula description =“In-line Formulas”end =“tail”？>，其提供了一种通过有利于成本降低的沉积工艺制造透明导电膜的方法，其可以在短时间内形成 透明导电膜具有不均匀的表面轮廓，具有高的光限制效应，并且当应用于形成光伏器件的多层结构时，可以实现光伏性能的提高并且获得高的批量生产率。

公开(公告)号：US06860974B2

公开(公告)日：2005-03-01

申请号：US10183339

申请日：2002-06-28

申请人： Hiroshi Echizen ,  Yasuyoshi Takai ,  Akiya Nakayama

发明人： Hiroshi Echizen ,  Yasuyoshi Takai ,  Akiya Nakayama

IPC分类号： C23C14/34 ,  C23C14/00 ,  C23C14/56 ,  H01L31/0224 ,  H01L31/04 ,  C23C14/32

CPC分类号： H01L31/022466 ,  C23C14/0042 ,  C23C14/0073 ,  C23C14/568 ,  H01L31/022483

摘要： There are provided techniques of forming a back reflecting layer with constant characteristics throughout long-term film formation and forming a metal oxide film so as to be able to maintain a current of a bottom cell and thereby keep a short-circuit current Jsc of a solar cell constant over a long period of time. A sputtering method is a method of forming a stack of a metal film and a metal oxide film, comprising the step 1 of forming a metal layer on a substrate, the step 2 of bringing a surface of the metal layer into contact with active oxygen, and the step 3 of forming a metal oxide film thereon after the step 2, wherein in the step 2 an amount of active oxygen at a first substrate position is different from that at a second substrate position.

摘要翻译： 提供了在长期成膜和形成金属氧化物膜时形成具有恒定特性的背反射层以便能够保持底电池的电流并由此保持太阳能的短路电流Jsc的技术 细胞常数长时间。 溅射法是形成金属膜和金属氧化物膜的堆叠的方法，其包括在基板上形成金属层的工序1，使金属层的表面与活性氧接触的工序2， 以及步骤2之后在其上形成金属氧化物膜的步骤3，其中在步骤2中，第一基板位置处的活性氧量与第二基板位置处的活性氧量不同。

公开(公告)号：US5597623A

公开(公告)日：1997-01-28

申请号：US307099

申请日：1994-09-16

申请人： Yasuyoshi Takai ,  Tetsuya Takei ,  Hirokazu Otoshi ,  Ryuji Okamura

发明人： Yasuyoshi Takai ,  Tetsuya Takei ,  Hirokazu Otoshi ,  Ryuji Okamura

IPC分类号： C23C16/50 ,  C23C16/511 ,  G03G5/08 ,  H01J37/32 ,  H01L21/205 ,  H05H1/30

CPC分类号： C23C16/511 ,  H01J37/32238 ,  H01J37/32467

摘要： An improved microwave plasma CVD process for forming a functional deposited film using a microwave transmissive window composed of a sintered alpha-alumina ceramics body containing alpha-alumina as a matrix comprised of fine particles with a mean particle size d satisfying the equation 0.5 .mu.m.ltoreq.d.ltoreq.50 .mu.m and with a ratio of .rho..sub.2 /.rho..sub.1 between the theoretical density .rho..sub.1 and the bulk density .rho..sub.2 satisfying the equation 0.800.ltoreq..rho..sub.2 /.rho..sub.1 .ltoreq.0.995.

摘要翻译： 一种改进的微波等离子体CVD法，用于使用由包含α-氧化铝的烧结α-氧化铝陶瓷体构成的微波透射窗形成功能性沉积膜，该α-氧化铝作为基质，其平均粒径d满足0.5μm / = d

公开(公告)号：US08624240B2

公开(公告)日：2014-01-07

申请号：US13188215

申请日：2011-07-21

申请人： Ayumu Sato ,  Hideya Kumomi ,  Hisato Yabuta ,  Ryo Hayashi ,  Yasuyoshi Takai

发明人： Ayumu Sato ,  Hideya Kumomi ,  Hisato Yabuta ,  Ryo Hayashi ,  Yasuyoshi Takai

IPC分类号： H01L29/786

CPC分类号： H01L29/7869 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648

摘要： Provided is a top gate thin film transistor, including on a substrate: a source electrode layer; a drain electrode layer; an oxide semiconductor layer; a gate insulating layer; a gate electrode layer including an amorphous oxide semiconductor containing at least one kind of element selected from among In, Ga, Zn, and Sn; and a protective layer containing hydrogen, in which: the gate insulating layer is formed on a channel region of the oxide semiconductor layer; the gate electrode layer is formed on the gate insulating layer; and the protective layer is formed on the gate electrode layer.

摘要翻译： 提供了一种顶栅薄膜晶体管，其包括在基板上：源电极层; 漏电极层; 氧化物半导体层; 栅极绝缘层; 包含含有选自In，Ga，Zn和Sn中的至少一种元素的非晶氧化物半导体的栅极电极层; 以及含有氢的保护层，其中：所述栅绝缘层形成在所述氧化物半导体层的沟道区上; 栅电极层形成在栅极绝缘层上; 并且在栅电极层上形成保护层。