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公开(公告)号：US11973052B2
公开(公告)日：2024-04-30
申请号：US17242380
申请日：2021-04-28
Applicant: Texas Instruments Incorporated
Inventor： Chien-Chang Li , Hung-Yu Chou , Sheng-Wen Huang , Zi-Xian Zhan , Byron Lovell Williams
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
CPC classification number: H01L24/48 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49575 , H01L24/85 , H01L2224/48137 , H01L2224/48245 , H01L2224/48465 , H01L2224/48479 , H01L2224/85051 , H01L2224/85205
Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
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公开(公告)号：US11848297B2
公开(公告)日：2023-12-19
申请号：US17364807
申请日：2021-06-30
Applicant: Texas Instruments Incorporated
Inventor： Bo-Hsun Pan , Chien-Chang Li , Hung-Yu Chou , Shawn Martin O'Connor , Byron Lovell Williams , Jeffrey Alan West , Zi-Xian Zhan , Sheng-Wen Huang
IPC: H01L23/00 , H01L23/495 , H01L25/065
CPC classification number: H01L24/48 , H01L23/4952 , H01L23/49575 , H01L24/45 , H01L24/85 , H01L25/0655 , H01L2224/45124 , H01L2224/45139 , H01L2224/45147 , H01L2224/45644 , H01L2224/45664 , H01L2224/48138 , H01L2224/48245 , H01L2224/48453 , H01L2224/48463 , H01L2224/48481 , H01L2224/85035 , H01L2224/85051 , H01L2924/182
Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.
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公开(公告)号：US11735506B2
公开(公告)日：2023-08-22
申请号：US16206640
申请日：2018-11-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hung-Yu Chou , Bo-Hsun Pan , Yuh-Harng Chien , Fu-Hua Yu , Steven Alfred Kummerl , Jie Chen , Rajen M. Murugan
IPC: H01L23/495 , H01L23/31 , H01L21/56 , H01L21/48
CPC classification number: H01L23/49568 , H01L21/4821 , H01L21/565 , H01L23/3107 , H01L23/49503
Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.
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公开(公告)号：US20200003548A1
公开(公告)日：2020-01-02
申请号：US16566140
申请日：2019-09-10
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hung-Yu Chou , Chien-Hao Wang , Tse-Tsun Chiu , Fu-Kang Lee , Liang-Kang Su
Abstract: A method for evaluating a leadframe surface includes positioning a leadframe on a measurement apparatus at a first predetermined distance relative to an end portion of a light source of an optical sensor; irradiating a predetermined area on a surface of the leadframe with light having a single predetermined wavelength from the light source; receiving, with a light receiver of the optical sensor, reflected light from the predetermined area on the surface of the leadframe, and converting the reflected light into an electric signal; determining a reflection intensity value of the predetermined area on the surface of the leadframe based on the electric signal; and calculating a reflection ratio of the predetermined area on the surface of the leadframe based on the reflection intensity value and a predetermined reference reflection intensity value associated with the light source.
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公开(公告)号：US10340152B1
公开(公告)日：2019-07-02
申请号：US15857988
申请日：2017-12-29
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Yuh-Harng Chien , Hung-Yu Chou , Fu-Kang Lee , Steven Alfred Kummerl
IPC: H01L23/495 , H01L21/48
CPC classification number: H01L21/4825 , H01L21/4842 , H01L23/49517 , H01L23/49548
Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.
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Patent Agency Ranking
公开(公告)号：US20240274570A1
公开(公告)日：2024-08-15
申请号：US18648632
申请日：2024-04-29
Applicant: Texas Instruments Incorporated
Inventor： Chien-Chang Li , Hung-Yu Chou , Sheng-Wen Huang , Zi-Xian Zhan , Byron Lovell Williams
IPC: H01L23/00 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/495
CPC classification number: H01L24/48 , H01L21/4825 , H01L21/565 , H01L23/3107 , H01L23/49513 , H01L23/4952 , H01L23/49575 , H01L24/85 , H01L2224/48137 , H01L2224/48245 , H01L2224/48465 , H01L2224/48479 , H01L2224/85051 , H01L2224/85205
Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
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公开(公告)号：US20240274569A1
公开(公告)日：2024-08-15
申请号：US18617449
申请日：2024-03-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bo-Hsun Pan , Hung-Yu Chou , Chung-Hao Lin , Yuh-Harng Chien
CPC classification number: H01L24/48 , H01L21/4828 , H01L21/565 , H01L23/28 , H01L24/29 , H01L24/32 , H01L2224/04042 , H01L2224/48091 , H01L2224/48177
Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
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公开(公告)号：US11942448B2
公开(公告)日：2024-03-26
申请号：US17377719
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bo-Hsun Pan , Hung-Yu Chou , Chung-Hao Lin , Yuh-Harng Chien
CPC classification number: H01L24/48 , H01L21/4828 , H01L21/565 , H01L23/28 , H01L24/29 , H01L24/32 , H01L2224/04042 , H01L2224/48091 , H01L2224/48177
Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
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公开(公告)号：US20230016577A1
公开(公告)日：2023-01-19
申请号：US17377719
申请日：2021-07-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Bo-Hsun Pan , Hung-Yu Chou , Chung-Hao Lin , Yuh-Harng Chien
Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
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公开(公告)号：US20220352111A1
公开(公告)日：2022-11-03
申请号：US17242380
申请日：2021-04-28
Applicant: Texas Instruments Incorporated
Inventor： Chien-Chang Li , Hung-Yu Chou , Sheng-Wen Huang , Zi-Xian Zhan , Byron Lovell Williams
IPC: H01L23/00 , H01L23/31 , H01L23/495 , H01L21/48 , H01L21/56
Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
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