公开(公告)号：US20230317571A1

公开(公告)日：2023-10-05

申请号：US17708038

申请日：2022-03-30

Applicant: Texas Instruments Incorporated

Inventor： Hsiang Ming Hsiao ,  Hung-Yu Chou ,  Yuh-Harng Chien ,  Chih-Chien Ho ,  Che Wei Tu ,  Bo-Hsun Pan ,  Megan Chang

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49555 ,  H01L21/56 ,  H01L21/4821 ,  H01L23/3107

Abstract: An electronic device with a conductive lead having an internal first section and an external second section extending outside a molded package structure, the first section having an obstruction feature extending vertically from a top or bottom side of the conductive lead and engaging a portion of the package structure to oppose movement of the conductive lead outward from the package structure.

公开(公告)号：US10861777B2

公开(公告)日：2020-12-08

申请号：US15856346

申请日：2017-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuh-Harng Chien ,  Hung-Yu Chou ,  Fu-Kang Lee

IPC: H01L23/495 ,  H01L23/544 ,  H01L23/00 ,  H01L25/065

Abstract: Aspects of the disclosure relate generally to semiconductor packaging, and specifically to semiconductor device having a lead frame having a semiconductor supporting die pad that is capable of engaging with a wire bonding clamp.

公开(公告)号：US11862538B2

公开(公告)日：2024-01-02

申请号：US17463124

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chung-Hao Lin ,  Hung-Yu Chou ,  Bo-Hsun Pan ,  Dong-Ren Peng ,  Pi-Chiang Huang ,  Yuh-Harng Chien

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/181

Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.

公开(公告)号：US20230005874A1

公开(公告)日：2023-01-05

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US11421981B2

公开(公告)日：2022-08-23

申请号：US16566140

申请日：2019-09-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hung-Yu Chou ,  Chien-Hao Wang ,  Tse-Tsun Chiu ,  Fu-Kang Lee ,  Liang-Kang Su

IPC: G01B11/06 ,  G01B11/30 ,  G01B11/28 ,  G01B11/16 ,  G01N21/00 ,  G01N21/55 ,  G01R31/00

Abstract: A method for evaluating a leadframe surface includes positioning a leadframe on a measurement apparatus at a first predetermined distance relative to an end portion of a light source of an optical sensor; irradiating a predetermined area on a surface of the leadframe with light having a single predetermined wavelength from the light source; receiving, with a light receiver of the optical sensor, reflected light from the predetermined area on the surface of the leadframe, and converting the reflected light into an electric signal; determining a reflection intensity value of the predetermined area on the surface of the leadframe based on the electric signal; and calculating a reflection ratio of the predetermined area on the surface of the leadframe based on the reflection intensity value and a predetermined reference reflection intensity value associated with the light source.

公开(公告)号：US20240113155A1

公开(公告)日：2024-04-04

申请号：US18146591

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Hung-Yu Chou ,  Byron Lovell Williams ,  Thomas Dyer Bonifield

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L28/10 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48245 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/49109 ,  H01L2924/1461 ,  H01L2924/3862

Abstract: A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.

公开(公告)号：US11948721B2

公开(公告)日：2024-04-02

申请号：US16883614

申请日：2020-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ying-Chuan Kao ,  Hung-Yu Chou ,  Dong-Ren Peng ,  Jun Jie Kuo ,  Kenji Otake ,  Chih-Chien Ho

IPC: H01F27/28 ,  H01F19/08 ,  H01L23/64 ,  H01L49/02

CPC classification number: H01F27/2804 ,  H01L23/645 ,  H01L28/10 ,  H01F2019/085 ,  H01F2027/2809

Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.

公开(公告)号：US11742265B2

公开(公告)日：2023-08-29

申请号：US16660713

申请日：2019-10-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hung-Yu Chou ,  Chi-Chen Chien ,  Yuh-Harng Chien ,  Steven Alfred Kummerl ,  Bo-Hsun Pan ,  Fu-Hua Yu

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49568 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/49548 ,  H01L23/49861 ,  H01L23/5228

Abstract: In some examples, a semiconductor package comprises a lead frame. The lead frame includes a first row of leads; a first pad coupled to the first row of leads; a second row of leads; and a second pad coupled to the second row of leads, the first and second pads separated by a gap. The semiconductor package includes a heat-generating device coupled to the first and second pads and exposed to an exterior of the semiconductor package.

公开(公告)号：US20210375525A1

公开(公告)日：2021-12-02

申请号：US16883614

申请日：2020-05-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ying-Chuan Kao ,  Hung-Yu Chou ,  Dong-Ren Peng ,  Jun Jie Kuo ,  Kenji Otake ,  Chih-Chien Ho

IPC: H01F27/28 ,  H01L23/64 ,  H01L49/02

Abstract: An apparatus includes a laminate, the laminate including a dielectric layer having a first surface and a second surface opposed to the first surface, and a conductive layer forming a circuit element overlying the first surface of the dielectric layer. The apparatus further includes a magnetic layer over the conductive layer. A first edge surface of the magnetic layer is coplanar with a first edge surface of the laminate, and a second edge surface of the magnetic layer is coplanar with a second edge surface of the laminate.

公开(公告)号：US12040197B2

公开(公告)日：2024-07-16

申请号：US17401057

申请日：2021-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yuh-Harng Chien ,  Hung-Yu Chou ,  Fu-Kang Lee ,  Steven Alfred Kummerl

IPC: H01L23/62 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L21/4825 ,  H01L21/4842 ,  H01L23/49517 ,  H01L23/49548 ,  H01L23/62 ,  H01L24/00 ,  H01L23/49551 ,  H01L23/49562

Abstract: An integrated circuit package having a shunt resistor with at least one self-aligning member that protrudes from a first surface, and a lead frame with at least one self-aligning feature that is a cavity within which the at least one self-aligning member is located, and an integrated circuit located on the lead frame.