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公开(公告)号：US20200044605A1
公开(公告)日：2020-02-06
申请号：US16601081
申请日：2019-10-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
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公开(公告)号：US09634736B2
公开(公告)日：2017-04-25
申请号：US15199611
申请日：2016-06-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Subhashish Mukherjee , Anoop Bhat , Kumar Anurag Shrivastava
CPC classification number: H04B5/0087 , H04B5/0031 , H04L27/04
Abstract: In described examples, a method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.
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公开(公告)号：US20240195417A1
公开(公告)日：2024-06-13
申请号：US18525464
申请日：2023-11-30
Applicant: Texas Instruments Incorporated
Inventor： Avinash Shah , Kashyap Barot , Sreeram Nasum S , Kumar Anurag Shrivastava , Suvadip Banerjee
IPC: H03K19/017 , G05B19/05 , H03K19/003 , H03K19/0185
CPC classification number: H03K19/01728 , G05B19/054 , H03K19/00361 , H03K19/00384 , H03K19/018557 , H03K19/017572
Abstract: An example apparatus includes: a current mirror having first and second outputs; oscillator circuitry including: a first transistor having a first terminal coupled to the first output of the current mirror, having a second terminal, and having a control terminal; and a second transistor having a first terminal coupled to the first output of the current mirror, having a second terminal coupled to the control terminal and the second terminal of the first transistor, and having a control terminal coupled to the second terminals of the first and second transistors; and current shunt circuitry having a terminal coupled to the second output of the current mirror.
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公开(公告)号：US20230069663A1
公开(公告)日：2023-03-02
申请号：US17446132
申请日：2021-08-26
Applicant: Texas Instruments Incorporated
Abstract: An example apparatus includes: a compensation circuit including: a current compensation output, a first transistor with a first current terminal and a first control terminal, the first current terminal coupled to the current compensation output, and a resistor ladder with a tap terminal coupled to the first control terminal, a current mirror circuit having a mirror input and a mirror output, the mirror input coupled to the current compensation output, and a rectification circuit having an input coupled to the mirror output.
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公开(公告)号：US10957655B2
公开(公告)日：2021-03-23
申请号：US16291042
申请日：2019-03-04
Applicant: Texas Instruments Incorporated
IPC: H01L23/552 , H01L23/544 , H01L23/00 , H01L27/01 , H01L49/02 , H01L21/70
Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.
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Patent Agency Ranking
公开(公告)号：US10804845B2
公开(公告)日：2020-10-13
申请号：US16601081
申请日：2019-10-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.
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公开(公告)号：US20200185336A1
公开(公告)日：2020-06-11
申请号：US16291042
申请日：2019-03-04
Applicant: Texas Instruments Incorporated
IPC: H01L23/552 , H01L23/544 , H01L23/00 , H01L27/01 , H01L49/02 , H01L21/70
Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.
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公开(公告)号：US20180006856A1
公开(公告)日：2018-01-04
申请号：US15200706
申请日：2016-07-01
Applicant: Texas Instruments Incorporated
CPC classification number: H04L27/22 , H03D3/00 , H03K19/21 , H03L7/081 , H03L7/087 , H03L7/113 , H04L7/0087 , H04L7/0331 , H04L27/2271
Abstract: Methods and apparatus for performing a high speed phase demodulation scheme using a low bandwidth phase-lock loop are disclosed. An example apparatus includes a low bandwidth phase lock loop to lock to a data signal at a first phase, the data signal capable of oscillating at the first phase or a second phase; and output a first output signal at the first phase and a second output signal at the second phase, the first output signal or the second output signal being utilized in a feedback loop of the low bandwidth phase lock loop. The example apparatus further includes a fast phase change detection circuit coupled to the low bandwidth phase lock loop to determine whether the data signal is oscillating at the first phase or the second phase; when the data signal is oscillating at the first phase, output a first logic value; and when the data signal is oscillating at the second phase, output a second logic value, the output of the fast phase change detection circuit being used to determine whether the first output signal or the second output signal will be utilized in the feedback loop of the low bandwidth phase lock loop.
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公开(公告)号：US09385790B1
公开(公告)日：2016-07-05
申请号：US14587817
申请日：2014-12-31
Applicant: Texas Instruments Incorporated
Inventor： Subhashish Mukherjee , Anoop Bhat , Kumar Anurag Shrivastava
CPC classification number: H04B5/0087 , H04B5/0031 , H04L27/04
Abstract: A method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset.
Abstract translation: 电感耦合通信的方法包括提供调谐到基本上相同的谐振频率的第一谐振回路（第一储罐）和第二谐振回路（第二储罐），每个谐振回路具有天线线圈和开关，用于改变其罐的Q和带宽 。 天线线圈分开一个提供近场通信的距离。 驱动第一坦克用于产生感应振荡以传送提供数据的预定数量的载波频率周期。 在预定数量的循环之后，启动开关以扩大第一箱的带宽。 响应于第一个罐中的振荡，第二个罐开始诱发振荡。 在检测到与感应振荡相关联的位时，启动开关以加宽第二箱的带宽，并且接收接收第二箱的输出的接收器电路被复位。
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公开(公告)号：US20240194583A1
公开(公告)日：2024-06-13
申请号：US18128490
申请日：2023-03-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kumar Anurag Shrivastava , Viresh Chinchansure
IPC: H01L23/522
CPC classification number: H01L23/5223 , H01L28/86 , H01L28/90
Abstract: An integrated circuit includes first second metal levels over a semiconductor substrate. A first capacitor electrode in the first metal level has a plurality of first lines. A second capacitor electrode in the first metal level includes a plurality of second lines alternating with the plurality of first metal lines. A third capacitor electrode in the second metal level includes a plurality of third lines. And a fourth capacitor electrode in the second metal level includes a plurality of fourth parallel lines alternating with the plurality of third metal lines. Each of the third lines is located over a first one of the first lines and a first one of the second lines, and each of the fourth lines is located over a second one of the first lines and a second one of the second lines.
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