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    Continuous time linear capacitive digital step attenuator
    14.
    发明授权
    Continuous time linear capacitive digital step attenuator 有权

    公开(公告)号：US10476542B1

    公开(公告)日：2019-11-12

    申请号：US16274621

    申请日：2019-02-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Neeraj Shrivastava ,  Rajendrakumar Joish ,  Shagun Dusad ,  Visvesvaraya Pentakota

    IPC: H04B1/04 ,  H04B1/18 ,  H03K17/94 ,  H03K19/173

    Abstract: A digital step attenuator (DSA) includes a switch control circuit which receives the attenuated signal output by the DSA from a buffer and generates a tracked control signal for switches within the DSA. Some switch control circuits include a capacitor coupled to receive the buffered signal, a supply voltage, and a switch control logic sub-circuit for each switch. Each switch control logic sub-circuit receives a control signal, for either the gate or the bulk terminal of the switch, and generates the tracked control signal. In other embodiments, switch control circuits include a complementary MOSFET switching device coupled to receive a control signal, and a capacitor coupled to receive the buffered signal, both of which are connected to an output terminal for the tracked control signal. In those embodiments, the DSA includes a switch control circuit for each switch connected to the DSA output.

    Top plate sampling circuit including input-dependent dual clock boost circuits
    15.
    发明授权
    Top plate sampling circuit including input-dependent dual clock boost circuits 有权

    公开(公告)号：US10439628B2

    公开(公告)日：2019-10-08

    申请号：US16104978

    申请日：2018-08-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ani Xavier ,  Neeraj Shrivastava ,  Arun Mohan

    IPC: H03M1/10 ,  H03M1/12 ,  G06F1/04

    Abstract: In some examples, a system includes a first transistor comprising a first source terminal coupled to a first input terminal, a first drain terminal coupled to a first top plate sampling capacitor, and a first gate terminal. The system also includes a first input-dependent dual clock boost circuit coupled to the first input terminal via a first boost circuit input and to the first gate terminal via a first boost circuit output. The system further includes a second transistor comprising a second source terminal coupled to a second input terminal, a second drain terminal coupled to a second top plate sampling capacitor, and a second gate terminal. The system also includes a second input-dependent dual clock boost circuit coupled to the second input terminal via a second boost circuit input and to the second gate terminal of the second transistor via a second boost circuit output.

    Analog-to-digital converter
    17.
    发明授权
    Analog-to-digital converter 有权

    公开(公告)号：US10200052B2

    公开(公告)日：2019-02-05

    申请号：US15859437

    申请日：2017-12-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Neeraj Shrivastava ,  Jafar Sadique Kaviladath

    IPC: H03M1/12 ,  H03M1/00 ,  H03M1/14 ,  H03M1/16

    Abstract: In some examples, a system comprises an analog-to-digital converter (ADC) to receive an analog input signal and a reset signal, the ADC to convert the analog input signal into a digital signal. The system comprises a digital-to-analog converter (DAC), coupled to the ADC, to convert the digital signal into an internal analog signal. The system includes a first capacitor, coupled to the DAC, to receive the internal analog signal. The system comprises a first switch, coupled to the first capacitor, to provide the analog input signal to the first capacitor. The system comprises a second switch to couple the first capacitor to ground.

    Noise-shaping of additive dither in analog-to-digital converters
    19.
    发明授权
    Noise-shaping of additive dither in analog-to-digital converters 有权

    公开(公告)号：US12224761B2

    公开(公告)日：2025-02-11

    申请号：US17729374

    申请日：2022-04-26

    Applicant: Texas Instruments Incorporated

    Inventor： Nithin Gopinath ,  Visvesvaraya A. Pentakota ,  Neeraj Shrivastava ,  Harshit Moondra

    IPC: H03M1/20 ,  H03M1/06

    Abstract: An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.

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