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公开(公告)号：US11296691B2
公开(公告)日：2022-04-05
申请号：US16867392
申请日：2020-05-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Amneh Mohammad Akour , Nikolaus Klemmer
Abstract: A power-on-reset (POR) circuit for CMOS logic is operable to transition between a POR_active state and a POR_inactive state and can include: (a) VDD/VT threshold circuitry to provide a Vtp_threshold voltage based on input Vdd and PMOS Vtp, and a Vtn_threshold voltage based on input Vdd and NMOS Vtn; (b) POR transition detect circuitry to provide a POR_transition signal (active/inactive) based on a function (Vtp, Vtn), which is a function of Vtp_threshold and Vtn_threshold; and (c) POR transition control circuitry to provide the POR_state signal (active/inactive) based on the POR_transition signal. For a POR out-of-reset transition, the POR transition detect circuitry to switch the POR_transition signal inactive based on the function (Vtp, Vtn) corresponding to the POR_inactive state, and the POR transition control circuitry, responsive to the POR_transition signal switching to inactive, to initiate a POR out-of-reset delay period, and to signal the POR_inactive state after the POR out-of-reset delay period.
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12.发明申请公开(公告)号：US20200259687A1
公开(公告)日：2020-08-13
申请号：US16515248
申请日：2019-07-18
Applicant: Texas Instruments Incorporated
Inventor： Nikolaus Klemmer , Amneh Mohammed Akour , Abhijit Anant Patki , Timothy Patrick Pauletti , Tarkesh Pande
Abstract: An integrated circuit includes a bit slicing circuit with a processing circuit. The processing circuit receives discrete frequency power estimates based on an S-FSK waveform received by an S-FSK receiver associated with the bit slicing circuit. The discrete frequency power estimates are representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. Each data frame including at least one word. Each word includes bit periods. The processing circuit receives SNR parameters that represent a dynamic SNR for the respective discrete frequency power estimates in relation to the series of data frames. The processing circuit selects a bit slicing technique from a set of available bit slicing techniques to generate data bit values for bit periods of the discrete frequency power estimates based on the SNR parameters. A method for performing bit slicing in an S-FSK receiver is also disclosed.
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公开(公告)号：US10536258B2
公开(公告)日：2020-01-14
申请号：US15996444
申请日：2018-06-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hunsoo Choo , Hamid Safiri , Nikolaus Klemmer , Jaimin Mehta , Srinadh Madhavapeddi , Charles Kasimer Sestok , Vijayavardhan Baireddy
Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.
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公开(公告)号：US20190372747A1
公开(公告)日：2019-12-05
申请号：US15996444
申请日：2018-06-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Hunsoo Choo , Hamid Safiri , Nikolaus Klemmer , Jaimin Mehta , Srinadh Madhavapeddi , Charles Kasimer Sestok , Vijayavardhan Baireddy
Abstract: Multi-domain clock generation with skew compensation is based on free-running counters in each of the multiple clock domains. Multi-domain clock generation circuitry provides at least first and second domain clocks generated with randomization, each based on an input clock with an input clock frequency, the domain clocks having a relative clock skew that is varied over time in magnitude and direction. A first circuit in a first clock domain, configured for operation with the first domain clock, includes a first free-running counter with a pre-defined first selected roll-over count, to generate a first free-running count (N1(k)) based on the first domain clock. A second circuit in a second clock domain is configured for operation with the second domain clock, and includes a second free-running counter with a pre-defined second selected roll-over count, to generate a second free-running count (N2(k)) based on the second domain clock.
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公开(公告)号：US10140229B2
公开(公告)日：2018-11-27
申请号：US14822175
申请日：2015-08-10
Applicant: Texas Instruments Incorporated
Inventor： Xiaoxi Zhang , Nikolaus Klemmer , Hunsoo Choo
IPC: G06F13/10 , G06F9/445 , G06F13/364 , G06F13/42 , G06F13/24
Abstract: Triggered remote function calls can be used in master-slave systems to trigger slave-side software functions pre-loaded by a master into slave MCU memory, with associated parameters pre-loaded into a slave function interface memory. A master issues trigger-function signals (such as rising/falling edges or signal levels) over a trigger-function signal line. The slave includes a trigger conditioning block that in response issues a trigger-function request to the slave MCU, which calls/executes the associated software function, including accessing the associated trigger-function parameters from function interface memory. A slave can include a hardware function block with functionality configurable by a pre-loaded software configuration function (with associated parameters). A master can include a hardware function block configured to issue trigger-function signals. The slave (trigger conditioning block) can be configured to service trigger-function signals as an IRQ (interrupt request) to the MCU, which executes an ISR (interrupt service routine) as a triggered function call.
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Patent Agency Ranking
公开(公告)号：US09998169B2
公开(公告)日：2018-06-12
申请号：US15466418
申请日：2017-03-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Charles Kasimer Sestok, IV , Hunsoo Choo , Nikolaus Klemmer , Xiaoxi Zhang
CPC classification number: H04B1/406 , H04B1/1027 , H04B1/403 , H04L7/0331
Abstract: A phase rotator corrects the IQ imbalance in a wireless transceiver. The phase rotator is a part of a compensation system that detects and separates reception impairment images from transmission impairment images. The disclosed phase rotator introduces a phase shift between the transmission channel and the reception channel without perturbing the phase mismatch and the gain mismatch in the reception path. The phase rotator includes a first local oscillation (LO) circuit that generates a first LO signal at a first carrier frequency and a second LO circuit that generates a second LO signal at a second carrier frequency that deviates from the first carrier frequency for a phase rotation period. The phase rotation period is sufficiently long such that the frequency deviation can introduce a prescribed phase shift between the first LO signal and the second LO signal.
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公开(公告)号：US20170187387A1
公开(公告)日：2017-06-29
申请号：US15455971
申请日：2017-03-10
Applicant: Texas Instruments Incorporated
Inventor： Venkatesh Srinivasan , Kun Shi , Victoria Wang , Nikolaus Klemmer
CPC classification number: H03M3/38 , H03K5/159 , H03M1/001 , H03M1/164 , H03M3/37 , H03M3/386 , H03M3/464
Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
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公开(公告)号：US10931488B2
公开(公告)日：2021-02-23
申请号：US14811618
申请日：2015-07-28
Applicant: Texas Instruments Incorporated
Inventor： Satish V. Uppathil , Nikolaus Klemmer , Fikret Dulger
IPC: H04B1/26 , H04M1/00 , H04L27/148 , H04B1/00
Abstract: A front-end receiver includes a first mixer of a first channel, a second mixer of a second channel, and a switching circuit that is configured to select the first mixer or the second mixer during a particular time period. Upon being selected, one of the first mixer or the second mixer is configured to deliver a down-converted signal that down-converts a respective RF signal of either the first or second reception channel. As the tasks of down-conversion and multiplexing are combined at the mixer level, the first and second reception channels may share a baseband circuit while being able to provide a well-balanced metrics of channel isolation, low noise figure, and linearity.
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19.发明授权公开(公告)号：US10797921B2
公开(公告)日：2020-10-06
申请号：US16450065
申请日：2019-06-24
Applicant: Texas Instruments Incorporated
IPC: H04L27/14 , H04L27/148 , H04B1/69
Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.
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20.发明申请公开(公告)号：US20200259690A1
公开(公告)日：2020-08-13
申请号：US16450065
申请日：2019-06-24
Applicant: Texas Instruments Incorporated
IPC: H04L27/148 , H04B1/69
Abstract: A threshold computation circuit includes an input circuit, a maximum filter circuit, a minimum filter circuit, and a calculating circuit. The input circuit receives a discrete frequency signal from a digital filtering circuit. The discrete frequency signal is based on an S-FSK waveform received by an S-FSK receiver associated with the digital filtering circuit. The discrete frequency signal is representative of digital logic levels in a series of data frames modulated using S-FSK to form the S-FSK waveform. The maximum filter circuit adjusts a maximum amplitude parameter based on the discrete frequency signal and a predetermined threshold. The minimum filter circuit adjusts a minimum amplitude parameter based on the discrete frequency signal and the predetermined threshold. The calculating circuit adapts the predetermined threshold for a next data frame based on the maximum and minimum amplitude parameters. An integrated circuit and a method for computing the threshold are also disclosed.
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