公开(公告)号：US20190295935A1

公开(公告)日：2019-09-26

申请号：US16427172

申请日：2019-05-30

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367 ,  H01L23/29

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals.A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

公开(公告)号：US09721859B2

公开(公告)日：2017-08-01

申请号：US14842535

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Andy Quang Tran ,  Alok Kumar Lohia ,  Reynaldo Corpuz Javier

IPC: H01L21/50 ,  H01L23/10 ,  H01L23/00 ,  H01L23/055

CPC classification number: H01L23/10 ,  H01L21/50 ,  H01L23/055 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/1631 ,  H01L2924/16315 ,  H01L2924/1659 ,  H01L2924/1679 ,  H01L2924/18301 ,  H01L2224/45099 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method of assembling a semi-hermetic semiconductor package includes bonding a semiconductor die having bond pads to a top side of a base region of a package substrate having vertical side walls that are hollow which define an inner open volume (gap) having an adhesive or thermoplastic material therein. There are a plurality of metal terminals providing top terminal contacts on the top side of the base region and bottom terminal contacts on a bottom side or below the base region. The bond pads are coupled to the top terminal contacts. A lid is placed which provides a top for the semiconductor package, where the lid extends to vertically oriented end protrusions so that the protrusions are positioned within the adhesive or thermoplastic material to secure the protrusions within the adhesive or thermoplastic material to provide a seal for the semiconductor package.

公开(公告)号：US09576886B1

公开(公告)日：2017-02-21

申请号：US15162807

申请日：2016-05-24

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/29

CPC classification number: H01L23/49582 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/09 ,  H01L24/29 ,  H01L24/46 ,  H01L24/97 ,  H01L2224/2908 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Abstract translation: 一种扁平无引线引线框架的引线框架，其在芯片焊盘上具有半导体管芯，端子和塑料封装，除了片材的背面之外，以提供暴露的热管芯焊盘，暴露的侧壁和暴露的背面 终端。 焊料可润湿的金属或金属合金镀层位于端子的背面和露出的壁上。 露出的热垫和端子的背面均包括缺少镀层的接触区域。

公开(公告)号：US09373569B1

公开(公告)日：2016-06-21

申请号：US14842460

申请日：2015-09-01

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H01L21/44 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31

CPC classification number: H01L23/49582 ,  H01L21/4821 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3675 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/09 ,  H01L24/29 ,  H01L24/46 ,  H01L24/97 ,  H01L2224/2908 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.

Abstract translation: 一种形成封装半导体器件的方法包括：提供一个平板无引线引线框架的引线框架片，其具有在芯片焊盘上的半导体管芯，端子和塑料封装，除了片材的背面以提供暴露的热管芯焊盘， 暴露在终端的背面。 锯条中的部分锯切从背面开始，通过终端在塑料封装内终止，以提供端子的暴露侧壁和塑料封装。 端子的暴露的热垫和暴露的背面全部短接在一起形成暴露的电互连金属表面（互连表面）。 互连的表面用可焊接的可润湿金属或金属合金镀层电镀。 互连的表面是去耦的。 在锯条中的第二次锯切完成了通过塑料封装的锯切，以提供单一化，形成多个封装的半导体器件。

公开(公告)号：US20150262918A1

公开(公告)日：2015-09-17

申请号：US14213042

申请日：2014-03-14

Applicant: Texas Instruments Incorporated

Inventor： Andy Quang Tran ,  Reynaldo Corpuz Javier ,  Alok Kumar Lohia

IPC: H01L23/495 ,  H01L23/24 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/432 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48095

Abstract: Semiconductor device package (100) comprises a metallic Quad Flat No-Lead/Small Outline No-Lead QFN/SON-type leadframe (101) with a pad (102) and a plurality of leads (103) with solderable surfaces (101a, 110a), at least one set of leads aligned in a row while having one surface in a common plane (170), each lead of the set having a protrusion (110) shaped as a metal sheet. A package material (160) encapsulates the assembly and the leadframe, the package material shaped by sidewalls (161) with the row of leads positioned along an edge of a sidewall and the protrusions extending away from the package sidewalls, the common-plane lead surfaces and the protrusions remaining un-encapsulated. The protruding metal sheets (110) are bent at an angle (171) from the common plane towards the package sidewalls.

Abstract translation: 半导体器件封装（100）包括具有焊盘（102）和多个具有可焊接表面（101a，110a）的引线（103）的金属四边形扁平无引脚/小外形无引线QFN / SON型引线框架 ），至少一组引线在一行中对准，同时在公共平面（170）中具有一个表面，该组的每个引线具有形成为金属片的突起（110）。 封装材料（160）封装组件和引线框架，封装材料由侧壁（161）成形，其中一排引线沿着侧壁的边缘定位，并且突出部远离封装侧壁延伸，共面引线表面 并且突起保持未封装。 突出的金属板（110）从公共平面朝向封装侧壁成一定角度（171）弯曲。

公开(公告)号：US20220092767A1

公开(公告)日：2022-03-24

申请号：US17544896

申请日：2021-12-07

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: G06T7/00 ,  H01L23/495 ,  H01L23/00

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

公开(公告)号：US09768098B2

公开(公告)日：2017-09-19

申请号：US15099864

申请日：2016-04-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00 ,  H01L29/06 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

公开(公告)号：US20160286652A1

公开(公告)日：2016-09-29

申请号：US14671727

申请日：2015-03-27

Applicant: Texas Instruments Incorporated

Inventor： Reynaldo Corpuz Javier ,  Alok Kumar Lohia ,  Andy Quang Tran

IPC: H05K1/18 ,  G06T7/00 ,  H04N7/18 ,  H05K3/30

CPC classification number: G06T7/0008 ,  H01L22/12 ,  H01L23/49503 ,  H01L23/49555 ,  H01L23/49568 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3421 ,  H05K2201/10689 ,  H05K2201/10969 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: An IC assembly including an exposed pad integrated circuit (“IC”) package having a thermal pad with a top surface and a bottom surface and with at least one peripheral surface portion extending transversely of and continuous with the bottom surface. The bottom surface and the at least one peripheral surface are exposed through a layer of mold compound. Also, methods of making an exposed pad integrated circuit (“IC”) package assembly. One method includes optically inspecting a solder bond bonding a thermal pad of an exposed pad IC package to a printed circuit board. Another method includes wave soldering an exposed pad of an IC package to a printed circuit board.

Abstract translation: 一种IC组件，其包括具有顶表面和底表面的热垫的暴露焊盘集成电路（“IC”）封装，以及至少一个横向并与底表面连续延伸的外围表面部分。 底表面和至少一个外围表面通过一层模具化合物暴露。 另外，制造裸露集成电路（“IC”）封装组件的方法。 一种方法包括光学检查焊接接合将暴露的焊盘IC封装的散热焊盘接合到印刷电路板。 另一种方法包括将IC封装的裸露焊盘波峰焊到印刷电路板上。

公开(公告)号：US20160233147A1

公开(公告)日：2016-08-11

申请号：US15099864

申请日：2016-04-15

Applicant: Texas Instruments Incorporated

Inventor： Alok Kumar Lohia ,  Reynaldo Corpuz Javier ,  Andy Quang Tran

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4952 ,  H01L21/4825 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/85 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device comprising a stack of semiconductor chips. The semiconductor chips have an electrically active side and an opposite electrically inactive side. The active sides bordered by an edge having first lengths and the inactive sides bordered by a parallel edge having a second lengths smaller than the first lengths. A substrate has an assembly pad bordered by a linear edge having a third length equal to or smaller than the first lengths. The inactive chip side attached to the pad so that the edge of the first lengths are parallel to the edge of the third length. The active side of the attached chip forms an overhang over the pad, when the third length is smaller than the first lengths.

Abstract translation: 一种包括半导体芯片堆叠的半导体器件。 半导体芯片具有电活动侧和相反的电不活动侧。 由具有第一长度的边缘接合的主动侧和由具有小于第一长度的第二长度的平行边缘接合的非活动侧。 衬底具有由具有等于或小于第一长度的第三长度的线性边缘界定的组装垫。 不活动的芯片侧附接到焊盘，使得第一长度的边缘平行于第三长度的边缘。 当第三长度小于第一长度时，附接芯片的活动侧在焊盘上形成突出部。

公开(公告)号：US20160005712A1

公开(公告)日：2016-01-07

申请号：US14854886

申请日：2015-09-15

Applicant: Texas Instruments Incorporated

Inventor： Andy Quang Tran ,  Reynaldo Corpuz Javier ,  Alok Kumar Lohia

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L24/97 ,  H01L21/4825 ,  H01L21/4835 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49555 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/432 ,  H01L2224/48091 ,  H01L2224/48096 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1711 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/48095

Abstract: A method for fabricating a semiconductor device package provides a metallic leadframes with a plurality of device sites. Each site including a pad and a plurality of leads with solderable surfaces. At least one set of leads are aligned in a row and are connected by rails to respective leads of an adjacent site. The leads and rails of the row having a surface in a common plane. The strip with the assembled sites and connecting rails are encapsulated in a packaging material, leaving the common-plane lead and rail surfaces un-encapsulated. Trenches are cut between adjacent sites by removing packaging material until reaching the rails. Thus, creating sidewalls of device packages connected by rails. Device packages are singulated from the strip by severing the connecting rails between adjacent sites in approximate halves, leaving a respective rail half as a straight protrusion attached to each lead. The protrusions are bent at an angle away from the common plane towards the package sidewall.

Abstract translation: 一种用于制造半导体器件封装的方法提供具有多个器件位置的金属引线框架。 每个场地包括一个焊盘和多个具有可焊接表面的引线。 至少一组引线被排列成一排，并且通过导轨连接到相邻位置的相应引线。 行的引线和轨道具有在公共平面中的表面。 具有组装位置和连接轨道的条带被封装在包装材料中，使共平面的引线和导轨表面未被封装。 通过移除包装材料直到到达轨道，在相邻位置之间切割沟槽。 因此，创建通过轨道连接的设备包的侧壁。 通过将相邻位置之间的连接轨道切割成近似一半，从条带中切割设备封装，留下相应的轨道半部，作为连接到每个引线的直的突起。 突起以与公共平面成一定角度朝向封装侧壁弯曲。