公开(公告)号：US20210119612A1

公开(公告)日：2021-04-22

申请号：US16943561

申请日：2020-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan MIGLANI ,  Shagun DUSAD

IPC: H03H11/12 ,  H03K19/20 ,  G06F1/10

Abstract: A circuit includes a filter, a first inverter, and a second inverter. The filter is coupled to an input of the first inverter. The second inverter includes an input and an output. The input of the second inverter is coupled to the output of the first inverter. The output of the second inverter is coupled to the input of the first inverter.

公开(公告)号：US20190273601A1

公开(公告)日：2019-09-05

申请号：US16417827

申请日：2019-05-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Srinivas Kumar Reddy NARU ,  Sarma Sundareswara GUNTURI ,  Nagalinga Swamy Basayya AREMALLAPUR

IPC: H04L7/00 ,  H03K5/14

Abstract: A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

公开(公告)号：US20180191472A1

公开(公告)日：2018-07-05

申请号：US15395783

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Nagarajan VISWANATHAN

IPC: H04L5/00 ,  H04B17/336

CPC classification number: H04B17/336 ,  H04B17/309 ,  H04L1/244 ,  H04L25/0202

Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.

公开(公告)号：US20170041019A1

公开(公告)日：2017-02-09

申请号：US15226436

申请日：2016-08-02

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Karthikeyan GUNASEKARAN ,  Santhosh Kumar GOWDHAMAN ,  Shagun DUSAD

IPC: H03M3/00

CPC classification number: H03M3/50 ,  H03M1/00 ,  H03M1/001 ,  H03M1/0626 ,  H03M1/0665 ,  H03M1/12 ,  H03M1/747 ,  H03M3/30 ,  H03M3/34 ,  H03M3/422 ,  H03M3/458 ,  H03M7/3004

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

Abstract translation: 本公开提供了包括第一输入端口和第二输入端口的Δ-Σ调制器。 这些端口接收差分输入信号。 DAC耦合到第一输入端口和第二输入端口，并且接收差分反馈信号和多个选择信号。 环路滤波器响应差分误差信号产生差分滤波信号。 差分误差信号与差分输入信号和差分反馈信号的差成比例。 量化器响应于差分滤波信号产生量化的输出信号。 耦合在量化器和DAC之间的经修改的DWA块响应于斩波时钟，规则时钟，量化的输出信号和多个选择索引信号产生多个选择信号。 选择索引信号取决于先前生成的多个选择信号。

公开(公告)号：US20220131551A1

公开(公告)日：2022-04-28

申请号：US17570658

申请日：2022-01-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sai Aditya Krishnaswamy NURANI ,  Joseph Palackal MATHEW ,  Prasanth K. ,  Visvesvaraya Appala PENTAKOTA ,  Shagun DUSAD

IPC: H03M1/12 ,  G11C27/02

Abstract: An example sample-and-hold circuit includes a first and second input resistors, each having first and second terminals; first and second transistors coupled in series between the second terminals of the first and second input resistors; and third and fourth input resistors, each having first and second terminals; and third and fourth transistors coupled in series between the second terminals of the third and fourth input resistors. The control terminals of the first and third transistors are coupled together, and the control terminals of the second and fourth transistors are coupled together.

公开(公告)号：US20210258018A1

公开(公告)日：2021-08-19

申请号：US17307684

申请日：2021-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Chirag Chandrahas SHETTY ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44

Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

公开(公告)号：US20200382128A1

公开(公告)日：2020-12-03

申请号：US16997975

申请日：2020-08-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Kumar Reddy NARU ,  Anand Jerry GEORGE ,  Shagun DUSAD ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/06 ,  H03M1/12 ,  H03M1/46

Abstract: A system has a digital-to-analog converter; a reference signal coupled to the digital-to-analog converter; a differential amplifier for applying gain, and for generating output signals as a function of sampled input signals, the reference signal, digital codes, and the gain applied by the differential amplifier coupled to the digital-to-analog converter; and a multi-bit successive-approximation register for determining the digital codes in successive stages coupled to the differential amplifier; and the gain applied by the differential amplifier is corrected based on previously determined digital codes.

公开(公告)号：US20200228127A1

公开(公告)日：2020-07-16

申请号：US16828149

申请日：2020-03-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Raja Reddy PATUKURI ,  Jagannathan VENKATARAMAN ,  Shagun DUSAD

IPC: H03M1/08 ,  H04B1/40 ,  H03M1/10

Abstract: A transceiver system includes a clock generator and an analog-to-digital circuit (ADC). The transceiver system also includes a coupling correction circuit coupled to the clock generator and to the ADC, wherein the coupling correction circuit is configured to provide an in-phase correction and a quadrature-phase correction to a signal received by the ADC.

公开(公告)号：US20190280703A1

公开(公告)日：2019-09-12

申请号：US16249225

申请日：2019-01-16

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy NARU ,  Narasimhan RAJAGOPAL ,  Shagun DUSAD ,  Viswanathan NAGARAJAN ,  Visvesvaraya Appala PENTAKOTA

IPC: H03M1/06 ,  H03M1/00 ,  H03M1/04

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

公开(公告)号：US20180191355A1

公开(公告)日：2018-07-05

申请号：US15395489

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun DUSAD ,  Visvesvaraya PENTAKOTA ,  Mark Baxter WEAVER ,  William BRIGHT ,  Jiankun HU

IPC: H03L7/08

CPC classification number: H03L7/08

Abstract: A system (and associated method) includes an input flip-flop, a counter, and a clock tree. The input flip-flop includes a clock input terminal configured to be coupled to a device clock, or a clock generated from a phase-locked loop, and a data input terminal configured to be coupled to a first reference signal. The input flip-flop is configured to use the device clock to latch the reference signal to produce a latched reference signal. The counter is configured to count pulses of the device clock starting upon detection of the latched reference signal and to output a second reference signal comprising a pulse for every L pulses of the device clock. The clock tree is configured to divide down the device clock to generate a first output clock. The clock tree is configured to be synchronized by a pulse of the second reference signal.