公开(公告)号：US10804845B2

公开(公告)日：2020-10-13

申请号：US16601081

申请日：2019-10-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Sreeram Subramanyam Nasum

IPC: H03B5/12 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  G06K19/077 ,  H02J50/12 ,  H01L25/10 ,  H04L25/02

Abstract: For communication across a capacitively coupled channel, an example circuit includes a first plate substantially parallel to a substrate, forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

公开(公告)号：US20200185336A1

公开(公告)日：2020-06-11

申请号：US16291042

申请日：2019-03-04

Applicant: Texas Instruments Incorporated

Inventor： Sreeram Subramanyam Nasum ,  Kumar Anurag Shrivastava ,  Jeffrey Alan West

IPC: H01L23/552 ,  H01L23/544 ,  H01L23/00 ,  H01L27/01 ,  H01L49/02 ,  H01L21/70

Abstract: An IC includes a substrate including metal levels thereon including a top and bottom metal level with at least a transmit (Tx) circuit and receive (Rx) circuit each having ≥1 isolation capacitor and an inductor. A scribe seal around the IC includes a first portion around the Tx circuit and second portion around the Rx circuit, utilizing ≥2 of the metal levels including at least an outer metal stack. The Tx and Rx circuits are side-by-side along a direction that defines a length for the scribe seal. The outer metal stack includes a neck region between the scribe seal portions including a shorting structure including metal level(s) for shorting together the outer metal stack of the scribe seal portions. An optional routing pass-through isolated from the shorting structure includes other metal layers connecting through the neck region between node(s) within the first and second scribe seal portion.

公开(公告)号：US20250079340A1

公开(公告)日：2025-03-06

申请号：US18951320

申请日：2024-11-18

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In some examples, a semiconductor device comprises a substrate, a trench, and a layer of a dielectric material. The substrate includes a semiconductor material and has opposing first and second surfaces. The trench extends between the first surface and the second surface, the trench having the dielectric material. The layer of the dielectric material is on the second surface of the substrate and is contiguous with the dielectric material in the trench.

公开(公告)号：US12148717B2

公开(公告)日：2024-11-19

申请号：US17583322

申请日：2022-01-25

Applicant: Texas Instruments Incorporated

Inventor： Scott Robert Summerfelt ,  Thomas Dyer Bonifield ,  Sreeram Subramanyam Nasum ,  Peter Smeys ,  Benjamin Stassen Cook

IPC: H01L23/00 ,  H01L21/762 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  H01L23/64

Abstract: In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

公开(公告)号：US11688672B2

公开(公告)日：2023-06-27

申请号：US17527994

申请日：2021-11-16

Applicant: Texas Instruments Incorporated

Inventor： Vijaylaxmi Khanolkar ,  Sreeram Subramanyam Nasum ,  Tarunvir Singh

IPC: H01L23/49 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L23/492

CPC classification number: H01L23/49589 ,  H01L21/565 ,  H01L23/492 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/46 ,  H01L24/85

Abstract: An electronic device having a package structure with conductive leads, first and second dies in the package structure, as well as first and second conductive plates electrically coupled to the respective first and second dies and having respective first and second sides spaced apart from and directly facing one another with a portion of the package structure extending between the first side of the first conductive plate and the second side of the second conductive plate to form a capacitor. No other side of the first conductive plate directly faces a side of the second conductive plate, and no other side of the second conductive plate directly faces a side of the first conductive plate.

公开(公告)号：US10819543B2

公开(公告)日：2020-10-27

申请号：US15354149

申请日：2016-11-17

Applicant: Texas Instruments Incorporated

Inventor： Sudhir Komarla Adinarayana ,  Sreenivasa S Mallia ,  Sreeram Subramanyam Nasum

IPC: H02H1/00 ,  H02H1/04 ,  H02H3/22 ,  H02H9/06 ,  H01C7/12 ,  H04L27/04 ,  H04B3/30 ,  H04B1/04 ,  H04B1/40 ,  H04B1/69

Abstract: An isolator chip includes a transmitter circuit coupled to provide differential output signals to respective first terminals of a first and a second capacitor and a receiver circuit coupled to receive the differential output signals from respective second terminals of the first and second capacitors. The transmitter circuit includes a voltage-clamping circuit coupled to receive an input signal and to provide a clamped signal, an oscillator coupled to receive the clamped signal and to provide the differential output signals, and a common mode transient immunity (CMTI) circuit that couples respective first terminals of the first and second capacitors to a lower rail responsive to the clamped signal being low.

公开(公告)号：US10447202B2

公开(公告)日：2019-10-15

申请号：US15427856

申请日：2017-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Sreeram Subramanyam Nasum

IPC: H03B5/12 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  G06K19/077 ,  H02J50/12 ,  H01L25/10

Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

公开(公告)号：US20180226920A1

公开(公告)日：2018-08-09

申请号：US15427856

申请日：2017-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Subhashish Mukherjee ,  Kumar Anurag Shrivastava ,  Sreeram Subramanyam Nasum

IPC: H03B5/12 ,  H03H1/00 ,  H03H7/01 ,  H01L23/00 ,  H01L23/31 ,  H01L23/64 ,  H01L25/07

Abstract: Apparatus for communication across a capacitively coupled channel are disclosed herein. An example circuit includes a first plate substantially parallel to a substrate, thereby forming a first capacitance intermediate the first plate and the substrate. A second plate is substantially parallel to the substrate and the first plate, the first plate intermediate the substrate and the second plate. A third plate is substantially parallel to the substrate, thereby forming a second capacitance intermediate the third plate and the substrate. A fourth plate is substantially parallel to the substrate and the third plate, the third plate intermediate the substrate and the fourth plate. An inductor is connected to the first plate and the third plate, the inductor to, in combination with the first capacitance and the second capacitance, form an LC amplifier.

公开(公告)号：US11841810B2

公开(公告)日：2023-12-12

申请号：US17244370

申请日：2021-04-29

Applicant: Texas Instruments Incorporated

Inventor： Suvadip Banerjee ,  Sreeram Subramanyam Nasum ,  Anant Shankar Kamath

IPC: G06F13/20 ,  G06F13/40 ,  H03K17/687 ,  G06F13/42

CPC classification number: G06F13/20 ,  G06F13/4086 ,  H03K17/6871 ,  G06F13/4282 ,  G06F2213/0016

Abstract: A communication interface buffer comprises: a data bus connection adapted to be coupled to a bus interface contact; and a ground. The communication interface buffer also comprises an output transistor with a first current terminal, a second current terminal and a control terminal, the first current terminal coupled to the data bus connection, the second current terminal coupled to ground, and the control terminal adapted to receive a drive signal. The communication interface buffer also comprises a control circuit coupled to the control terminal of the output transistor, wherein the control circuit is configured to: turn off the output transistor during a first interval that starts when the data bus connection is coupled to the bus interface contact; and turn on the output transistor after the first interval is complete.

公开(公告)号：US11552619B2

公开(公告)日：2023-01-10

申请号：US17377087

申请日：2021-07-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kashyap Jayendra Barot ,  Suvadip Banerjee ,  Sreeram Subramanyam Nasum

IPC: H03K3/0233 ,  H02M1/00 ,  H02M3/335 ,  H02M1/08 ,  H02M1/14

Abstract: An apparatus includes a first control circuit having an output and including a first comparator and a second control circuit coupled to the output of the first control circuit. The second control circuit includes a second comparator configured to: compare a first value to a reference frequency value, the first value indicating a frequency of a signal at the output of the first control circuit; and provide an adjustment value to change a hysteresis window of the first comparator.