公开(公告)号：US09818757B2

公开(公告)日：2017-11-14

申请号：US15072722

申请日：2016-03-17

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Kiwamu Sakuma ,  Masumi Saitoh

IPC: H01L29/10 ,  H01L27/115 ,  H01L29/24 ,  H01L27/11582 ,  H01L21/28 ,  H01L29/786 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/11575

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11575 ,  H01L29/7869 ,  H01L29/7926

Abstract: This semiconductor device comprises a plurality of first conductive layers arranged above a substrate in a first direction intersecting an upper surface of the substrate. The conductive layers includes a portion in which positions of ends of the first conductive layers made different from each other in a second direction intersecting the first direction. Furthermore, this semiconductor device comprises a transistor electrically connected to the portion of the conductive layers. That transistor comprises: a channel layer extending in the first direction; a gate electrode layer disposed in a periphery of the channel layer; and a gate insulating layer disposed between the channel layer and the gate electrode layer.

公开(公告)号：US20200302993A1

公开(公告)日：2020-09-24

申请号：US16567919

申请日：2019-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika Tanaka ,  Keiji Ikeda

IPC: G11C11/4097 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/404 ,  G11C11/4099

Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.

公开(公告)号：US10431287B2

公开(公告)日：2019-10-01

申请号：US15705864

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Chika Tanaka ,  Keiji Ikeda

IPC: G11C11/404 ,  G11C11/4096 ,  G06N3/04 ,  H01L27/12 ,  H01L27/108 ,  G11C11/56 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/54

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell including a transistor formed of an oxide semiconductor, an insulation film, and a control electrode, and a capacitance element configured to store a charge, the memory cell being configured to store a coupling weight of a neuron model by a charge amount accumulated in the capacitance element; and a control circuit configured to output a signal as a sum of a product between input data of the memory cell and the coupling weight.

公开(公告)号：US10332581B2

公开(公告)日：2019-06-25

申请号：US15916427

申请日：2018-03-09

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Chika Tanaka ,  Toshinori Numata ,  Tsutomu Tezuka

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/403 ,  G11C11/408

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell including a first transistor and a first capacitor, a second memory cell including a second transistor and a second capacitor, a first word line electrically coupled to the first transistor, a second word line electrically coupled to the second transistor, and a first circuit which supplies a first voltage to the first word line, and a second voltage different from the first voltage to the second word line, during a sleep mode.

公开(公告)号：US10192876B2

公开(公告)日：2019-01-29

申请号：US15698077

申请日：2017-09-07

Applicant: Toshiba Memory Corporation

Inventor： Kentaro Miura ,  Tomomasa Ueda ,  Keiji Ikeda ,  Nobuyoshi Saito

IPC: H01L27/00 ,  H01L27/11524 ,  H01L27/12 ,  H01L29/786

Abstract: According to one embodiment, a transistor includes: a gate electrode; a gate insulating layer provided on the gate electrode; an oxide semiconductor layer provided on the gate insulating layer; an oxygen supply layer provided on the oxide semiconductor layer; a first oxygen barrier layer provided on the oxygen supply layer; a source electrode provided to penetrate the oxygen supply layer and the first oxygen barrier layer and connected to the oxide semiconductor layer; and a drain electrode spaced apart from the source electrode, provided to penetrate the oxygen supply layer and the first oxygen barrier layer, and connected to the oxide semiconductor layer.

公开(公告)号：US20180269210A1

公开(公告)日：2018-09-20

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu TEZUKA ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/10802 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  H01L27/10847 ,  H01L27/10897 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.

公开(公告)号：US10043808B1

公开(公告)日：2018-08-07

申请号：US15705457

申请日：2017-09-15

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: H01L29/76 ,  H01L27/105 ,  H01L29/792 ,  H01L29/786 ,  G11C11/4097 ,  H01L29/423

Abstract: According to one embodiment, a semiconductor memory includes: a first gate of a first select transistor and a second gate of a second select transistor on a gate insulating film on a semiconductor layer; an oxide semiconductor layer above the semiconductor layer; a first control gate of a first cell and a second control gate of a second cell on an insulating layer on the oxide semiconductor layer; a third gate of a first transistor between the first control gate and the second control gate; a fourth gate of a second transistor between a first end of the oxide semiconductor layer and the second control gate; an interconnect connected to the first end; a source line connected to the first select transistor; and a bit line connected to the second select transistor.

公开(公告)号：US10950295B2

公开(公告)日：2021-03-16

申请号：US16567919

申请日：2019-09-11

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Chika Tanaka ,  Keiji Ikeda

IPC: G11C11/4097 ,  G11C11/4076 ,  G11C11/4099 ,  G11C11/404 ,  G11C11/4091

Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.

公开(公告)号：US10608009B2

公开(公告)日：2020-03-31

申请号：US15067830

申请日：2016-03-11

Applicant: Toshiba Memory Corporation

Inventor： Keiji Ikeda ,  Masumi Saitoh ,  Hideaki Aochi ,  Takeshi Kamigaichi ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157

Abstract: This nonvolatile semiconductor memory device comprises: a memory cell array including memory cells; and a wiring line portion connecting the memory cell array to an external circuit. The memory cell array comprises a plurality of first conductive layers which are connected to the memory cells and arranged in a stacking direction. On the other hand, the wiring line portion comprises: a plurality of second conductive layers arranged in the stacking direction and respectively connected to the plurality of first conductive layers, positions of ends of the plurality of second conductive layers being different in a first direction crossing the stacking direction; a third conductive layer extending in the stacking direction from the second conductive layer; a channel semiconductor layer connected to one end of the third conductive layer; and a gate electrode wiring line disposed on a surface of the channel semiconductor layer via a gate insulating film.

公开(公告)号：US10312239B2

公开(公告)日：2019-06-04

申请号：US15704643

申请日：2017-09-14

Applicant: Toshiba Memory Corporation

Inventor： Tsutomu Tezuka ,  Fumitaka Arai ,  Keiji Ikeda ,  Tomomasa Ueda ,  Nobuyoshi Saito ,  Chika Tanaka ,  Kentaro Miura

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  H01L27/12 ,  H01L27/108 ,  H01L29/786 ,  H01L27/1156 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: According to one embodiment, a memory includes: a bit line; a source line; a pillar extending in a first direction and including an oxide semiconductor layer; first, second and third layers arranged along the first direction and opposed to a side of the pillar; a memory cell at an intersection between the first layer and the pillar, the memory cell including a charge storage layer in the oxide semiconductor layer; a first transistor at an intersection between the second layer and the pillar; and a second transistor at an intersection between the third layer and the pillar. A first end of the oxide semiconductor layer in the first direction is in contact with the source line, and a second end of the oxide semiconductor layer in the first direction is electrically disconnected from the bit line.