公开(公告)号：US20220013652A1

公开(公告)日：2022-01-13

申请号：US16925718

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Chan-Lon Yang ,  Keh-Jeng Chang

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L27/088 ,  H01L21/822 ,  H01L21/8234

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

公开(公告)号：US20210376137A1

公开(公告)日：2021-12-02

申请号：US16885850

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David YANG ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

公开(公告)号：US11075282B2

公开(公告)日：2021-07-27

申请号：US16689033

申请日：2019-11-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An Liu ,  Chan-Lon Yang ,  Bharath Kumar Pulicherla ,  Zhi-Qiang Wu ,  Chung-Cheng Wu ,  Chih-Han Lin ,  Gwan-Sin Chang

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A method includes forming a gate layer over a semiconductor fin; forming a patterned mask over the gate layer; performing a first etching process to pattern the gate layer using the patterned mask as an etch mask, the patterned gate layer comprising a first gate extending across the semiconductor fin; depositing, by using an directional ion beam, a protection layer to wrap around a top surface, a first sidewall and a second sidewall of the first gate, the protection layer extending along the first and second sidewalls of the first gate towards a bottom surface of the first gate without extending to the bottom surface of the first gate on the second sidewall of the first gate; and after depositing the protection layer, performing a second etching process to a portion of the second sidewall of the first gate exposed by the protection layer.

公开(公告)号：US10749029B2

公开(公告)日：2020-08-18

申请号：US16226276

申请日：2018-12-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kun-Mu Li ,  Tsz-Mei Kwok ,  Ming-Hua Yu ,  Chan-Lon Yang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L21/3115 ,  H01L27/12 ,  H01L29/66 ,  H01L29/165

Abstract: A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions.

公开(公告)号：US12211918B2

公开(公告)日：2025-01-28

申请号：US18231486

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang ,  Perng-Fei Yuh

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US12027583B2

公开(公告)日：2024-07-02

申请号：US17320170

申请日：2021-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang ,  Perng-Fei Yuh

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

公开(公告)号：US11869954B2

公开(公告)日：2024-01-09

申请号：US17334541

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang ,  Perng-Fei Yuh

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78696

Abstract: A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

公开(公告)号：US11749756B2

公开(公告)日：2023-09-05

申请号：US17074287

申请日：2020-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Yu Lin ,  Ming-Hua Yu ,  Tze-Liang Lee ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L23/544 ,  H01L21/265 ,  H01L21/324 ,  H01L29/06 ,  H01L29/10 ,  H01L29/167

CPC classification number: H01L29/7851 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/544 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2223/54426 ,  H01L2223/54453

Abstract: A method includes forming an implanted region in a substrate. The implanted region is adjacent to a top surface of the substrate. A clean treatment is performed on the top surface of the implanted region. The top surface of the implanted region is baked after the clean treatment. An epitaxial layer is formed on the top surface of the substrate. The epitaxial layer is patterned to form a fin.

公开(公告)号：US20230223460A1

公开(公告)日：2023-07-13

申请号：US18175180

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L29/66553 ,  H01L29/408 ,  H01L29/7853 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6681 ,  H01L29/4908 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/42392 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/31116

Abstract: The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

公开(公告)号：US11335606B2

公开(公告)日：2022-05-17

申请号：US16997062

申请日：2020-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chansyun David Yang ,  Keh-Jeng Chang ,  Chan-Lon Yang

IPC: H01L21/84 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/12 ,  H01L21/762

Abstract: The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.