公开(公告)号：US11728233B2

公开(公告)日：2023-08-15

申请号：US16941847

申请日：2020-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Po-Chen Lai ,  Kuang-Chun Lee ,  Che-Chia Yang ,  Chin-Hua Wang ,  Yi-Hang Lin

IPC: H01L23/24 ,  H01L23/498 ,  H01L25/18 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/24 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/15311

Abstract: A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

公开(公告)号：US20220384313A1

公开(公告)日：2022-12-01

申请号：US17818729

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20220037243A1

公开(公告)日：2022-02-03

申请号：US17126598

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

公开(公告)号：US10790164B1

公开(公告)日：2020-09-29

申请号：US16439944

申请日：2019-06-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Yi Lin ,  Che-Chia Yang ,  Kuang-Chun Lee ,  Yu-Sheng Lin ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065 ,  H01L23/29

Abstract: A method for forming a package structure is provided. The method includes forming a first die over a first substrate, and injecting a molding compound material from a first side of the first die to a second side of the first die. The molding compound material includes a plurality of first fillers, each of the first fillers has a length along a longitudinal axis and a width along a transverse direction, and the length is greater than the width. The method further includes heating the molding compound material to form a package layer over the first die, and the first fillers are substantially parallel to each other.

公开(公告)号：US12148684B2

公开(公告)日：2024-11-19

申请号：US17126598

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

公开(公告)号：US20240371783A1

公开(公告)日：2024-11-07

申请号：US18778258

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US12100664B2

公开(公告)日：2024-09-24

申请号：US18352595

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/561 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/06 ,  H01L24/09 ,  H01L24/20 ,  H01L24/30 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/072 ,  H01L21/486 ,  H01L23/3128

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US12094828B2

公开(公告)日：2024-09-17

申请号：US17126881

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chia-Kuei Hsu ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/5384 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/14

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line including a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes depositing a conductive material into the via opening to form a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, and the second via is offset from a center line of the conductive bump.

公开(公告)号：US11855008B2

公开(公告)日：2023-12-26

申请号：US17818729

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Shen Yeh ,  Che-Chia Yang ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng ,  Chia-Hsiang Lin

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3185 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

公开(公告)号：US20210335753A1

公开(公告)日：2021-10-28

申请号：US17028629

申请日：2020-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.