公开(公告)号：US11158539B2

公开(公告)日：2021-10-26

申请号：US16589941

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

IPC: H01L21/768 ,  H01L21/265 ,  H01L23/532 ,  H01L23/535

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.

公开(公告)号：US12216407B2

公开(公告)日：2025-02-04

申请号：US18114690

申请日：2023-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Hsuan Chuang ,  Po-Sheng Lu ,  Shou-Wen Kuo ,  Cheng-Yi Huang ,  Chia-Hung Chu

IPC: G03F7/16 ,  G03F7/004 ,  H01L21/027

Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.

公开(公告)号：US20240347342A1

公开(公告)日：2024-10-17

申请号：US18756008

申请日：2024-06-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Hung-Yi Huang ,  Yu-Yun Peng ,  Mrunal A. Khaderbad ,  Chia-Hung Chu ,  Shuen-Shin Liang ,  Keng-Chu Lin

IPC: H01L21/265 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/26586 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76895 ,  H01L23/53209 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/535

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

公开(公告)号：US12068252B2

公开(公告)日：2024-08-20

申请号：US17875675

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Wei Chang ,  Chien-Shun Liao ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Shu-Lan Chang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53266 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76883 ,  H01L23/5283 ,  H01L23/53238

Abstract: The present disclosure describes a method for the fabrication of ruthenium conductive structures over cobalt conductive structures. In some embodiments, the method includes forming a first opening in a dielectric layer to expose a first cobalt contact and filling the first opening with ruthenium metal to form a ruthenium contact on the first cobalt contact. The method also includes forming a second opening in the dielectric layer to expose a second cobalt contact and a gate structure and filling the second opening with tungsten to form a tungsten contact on the second cobalt contact and the gate structure. Further, the method includes forming a copper conductive structure on the ruthenium contact and the tungsten contact, where the copper from the copper conductive structure is in contact with the ruthenium metal from the ruthenium contact.

公开(公告)号：US12002867B2

公开(公告)日：2024-06-04

申请号：US17459494

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hung Chu ,  Shuen-Shin Liang ,  Hsu-Kai Chang ,  Tzu Pei Chen ,  Kan-Ju Lin ,  Chien Chang ,  Hung-Yi Huang ,  Sung-Li Wang

IPC: H01L29/45 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/31116 ,  H01L21/823475 ,  H01L23/53242 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

公开(公告)号：US11972974B2

公开(公告)日：2024-04-30

申请号：US17575444

申请日：2022-01-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Sung-Li Wang ,  Shuen-Shin Liang ,  Yu-Yun Peng ,  Fang-Wei Lee ,  Chia-Hung Chu ,  Mrunal Abhijith Khaderbad ,  Keng-Chu Lin

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/02068 ,  H01L21/28562 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53252 ,  H01L23/53266

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

公开(公告)号：US11837544B2

公开(公告)日：2023-12-05

申请号：US17815730

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53242

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20230387017A1

公开(公告)日：2023-11-30

申请号：US18232722

申请日：2023-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsu-Kai Chang ,  Keng-Chu Lin ,  Sung-Li Wang ,  Shuen-Shin Liang ,  Chia-Hung Chu

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/53257 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53242

Abstract: The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

公开(公告)号：US20220367660A1

公开(公告)日：2022-11-17

申请号：US17320553

申请日：2021-05-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chih-Chien Chi ,  Chien-Shun Liao ,  Keng-Chu Lin ,  Kai-Ting Huang ,  Sung-Li Wang ,  Yi-Ying Liu ,  Chia-Hung Chu ,  Hsu-Kai Chang ,  Cheng-Wei Chang

IPC: H01L29/45 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/768

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

公开(公告)号：US11476365B2

公开(公告)日：2022-10-18

申请号：US16744480

申请日：2020-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Sung-Li Wang ,  Fang-Wei Lee ,  Jung-Hao Chang ,  Mrunal Abhijith Khaderbad ,  Keng-Chu Lin

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/45 ,  H01L21/311 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/3213

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes growing a source/drain epitaxial structure over the fin structure. The method also includes depositing a first dielectric layer surrounding the source/drain epitaxial structure. The method also includes forming a contact structure in the first dielectric layer over the source/drain epitaxial structure. The method also includes depositing a second dielectric layer over the first dielectric layer. The method also includes forming a hole in the second dielectric layer to expose the contact structure. The method also includes etching the contact structure to enlarge the hole in the contact structure. The method also includes filling the hole with a conductive material.