公开(公告)号：US10707315B2

公开(公告)日：2020-07-07

申请号：US16390515

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Henry Kwong ,  Chih-Yung Lin ,  Po-Nien Chen ,  Chen Hua Tsai

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US20200097632A1

公开(公告)日：2020-03-26

申请号：US16414488

申请日：2019-05-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Jeff Lin ,  Chih-Yung Lin ,  Dian-Sheg Yu ,  Hsiao-Lan Yang ,  Jhon Jhy Liaw

IPC: G06F17/50 ,  H01L27/088 ,  H01L29/78 ,  H01L23/522 ,  H01L21/8234

Abstract: The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.

公开(公告)号：US10312334B2

公开(公告)日：2019-06-04

申请号：US15141951

申请日：2016-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Henry Kwong ,  Chih-Yung Lin ,  Po-Nien Chen ,  Chen Hua Tsai

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US20250169163A1

公开(公告)日：2025-05-22

申请号：US19030103

申请日：2025-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Han Liu ,  Hoppy Lee ,  Chung-Yu Chiang ,  Po-Nien Chen ,  Chih-Yung Lin

IPC: H10D84/80 ,  H01L21/033 ,  H01L21/768 ,  H10D1/68 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

公开(公告)号：US11908896B2

公开(公告)日：2024-02-20

申请号：US17859731

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/0847 ,  H01L21/02381 ,  H01L21/02579 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/41791

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US20220352318A1

公开(公告)日：2022-11-03

申请号：US17859731

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tap cell surrounding the IC cell; forming first fin active regions in the well tap cell and second fin active regions in the IC cell; forming a hard mask within the well tap cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tap cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tap cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tap cell.

公开(公告)号：US11024703B2

公开(公告)日：2021-06-01

申请号：US16914528

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chiun Lin ,  Po-Nien Chen ,  Chen Hua Tsai ,  Chih-Yung Lin

IPC: H01L23/522 ,  H01L29/66 ,  H01L49/02 ,  H01L29/10 ,  H01L27/02 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

公开(公告)号：US20200243396A1

公开(公告)日：2020-07-30

申请号：US16853474

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ta-Chun Lin ,  Buo-Chin Hsu ,  Kuo-Hua Pan ,  Jhon Jhy Liaw ,  Chih-Yung Lin

IPC: H01L21/8234 ,  H01L29/06 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

公开(公告)号：US10665673B2

公开(公告)日：2020-05-26

申请号：US16263656

申请日：2019-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Jeng-Ya Yeh ,  Chih-Yung Lin

IPC: H01L21/02 ,  H01L29/02 ,  H01L29/08 ,  H01L29/417 ,  H01L21/324 ,  H01L21/762 ,  H01L21/306

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell.

公开(公告)号：US20200006467A1

公开(公告)日：2020-01-02

申请号：US16021662

申请日：2018-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiefeng Lin ,  Hsiao-Lan Yang ,  Chih-Yung Lin

IPC: H01L49/02 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768 ,  H01L27/06

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.