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    Semiconductor package structure
    12.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US11004810B2

    公开(公告)日：2021-05-11

    申请号：US16714768

    申请日：2019-12-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Nan-Chin Chuang

    IPC: H01L23/66 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01Q21/06 ,  H01Q1/22 ,  H01L23/31 ,  H01L21/683 ,  H01Q21/28 ,  H01Q1/40

    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

    Semiconductor package structure
    14.
    发明授权
    Semiconductor package structure 有权

    公开(公告)号：US10510693B2

    公开(公告)日：2019-12-17

    申请号：US15717940

    申请日：2017-09-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kai-Chiang Wu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Nan-Chin Chuang

    IPC: H01L23/66 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01Q21/06 ,  H01Q1/22 ,  H01L23/31

    Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

    Package structure having connecting module
    15.
    发明授权
    Package structure having connecting module 有权

    公开(公告)号：US10381309B2

    公开(公告)日：2019-08-13

    申请号：US15965980

    申请日：2018-04-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Albert Wan

    IPC: H01L23/538 ,  H01L23/498 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00

    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.

    INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF
    20.
    发明申请
    INTEGRATED FAN-OUT PACKAGE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20200152570A1

    公开(公告)日：2020-05-14

    申请号：US16706805

    申请日：2019-12-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Lin Lu ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Nan-Chin Chuang

    IPC: H01L23/522 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00

    Abstract: An integrated fan-out (InFO) package includes a first redistribution structure, a die, an encapsulant, a plurality of first through interlayer vias (TIV), a second redistribution structure, an insulating layer, a supporting layer, and a plurality of conductive patches. The die is disposed on the first redistribution structure. The encapsulant encapsulates the die. The first TIVs are embedded in the encapsulant. The second redistribution structure is disposed on the die, the first TIVs, and the encapsulant. The first redistribution structure is electrically connected to the second redistribution structure through the first TIVs. The insulating layer is disposed on the first redistribution structure opposite to the die and includes a plurality of air gaps. The supporting layer is over the insulating layer. The conductive patches are over the supporting layer. Locations of the conductive patches correspond to locations of the air gaps of the insulating layer.

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