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    MEMORY DEVICE WITH STABLE WRITING AND/OR READING OPERATION
    11.
    发明申请
    MEMORY DEVICE WITH STABLE WRITING AND/OR READING OPERATION 有权
    具有稳定写入和/或读取操作的存储器件

    公开(公告)号：US20160322098A1

    公开(公告)日：2016-11-03

    申请号：US14700135

    申请日：2015-04-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Mohammed HASAN TAUFIQUE ,  Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C11/412

    Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

    Abstract translation: 存储器件包括第一反相器，与第一反相器交叉耦合的第二反相器，存取单元和切换单元。 访问单元被配置为对第一反相器的输出进行放电，并根据由第一字线和第二字线提供的信号对第二反相器的输出进行充电。 开关单元被配置为根据由第一字线提供的信号来断开来自第一逆变器和第二逆变器的电力。

    MEMORY DEVICE
    13.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210398589A1

    公开(公告)日：2021-12-23

    申请号：US17035118

    申请日：2020-09-28

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Yi-Hsin NIEN ,  Wei-Chang ZHAO ,  Chih-Yu LIN ,  Hidehiro FUJIWARA ,  Yen-Huei CHEN ,  Ru-Yu WANG

    IPC: G11C11/419 ,  G11C11/412 ,  G11C5/06

    Abstract: A memory device includes a first program line and a second program line. A first portion of the first program line is formed in a first conductive layer, and a second portion of the first program line is formed in a second conductive layer above the first conductive layer. A first portion of the second program line is formed in the first conductive layer. A second portion of the second program line is formed in the second conductive layer. A third portion of the second program line is formed in a third conductive layer above the second conductive layer. The first portion and the second portion of the first program line have sizes that are different from each other, and the first portion, the second portion and the third portion of the second program line have sizes that are different from each other.

    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
    14.
    发明申请
    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS 有权

    公开(公告)号：US20210265363A1

    公开(公告)日：2021-08-26

    申请号：US17320091

    申请日：2021-05-13

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: H01L27/11 ,  H01L27/02 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528

    Abstract: A device is disclosed that includes a fin structure disposed below a first metal layer, extending along a column direction, and corresponding to at least one transistor of a memory bit cell, a word line disposed in the first metal layer and extending along a row direction, a first metal island disposed in the first metal layer separated from the word line, and a first connection metal line disposed in a second metal layer above the first metal layer, extending along the column direction, and configured to couple a power supply through the first metal island to the fin structure. In a layout view, the first connection metal line is separated from the fin structure, and the fin structure crosses over the word line and the first metal island. A method is also disclosed herein.

    BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE
    15.
    发明申请
    BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE 有权

    公开(公告)号：US20210183418A1

    公开(公告)日：2021-06-17

    申请号：US17128831

    申请日：2020-12-21

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Yen-Huei CHEN

    IPC: G11C7/12 ,  G11C5/14 ,  H03K19/003 ,  G11C7/10 ,  G11C7/08

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

    MEMORY CELL
    17.
    发明申请
    MEMORY CELL 审中-公开

    公开(公告)号：US20180151226A1

    公开(公告)日：2018-05-31

    申请号：US15799253

    申请日：2017-10-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Hung-Jen LIAO ,  Hsien-Yu PAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Chien-Chen LIN

    IPC: G11C15/04 ,  H01L27/02

    Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
    18.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT 有权

    公开(公告)号：US20220383947A1

    公开(公告)日：2022-12-01

    申请号：US17818386

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Sahil Preet Singh ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: G11C11/419 ,  G11C11/412

    Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

    BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE
    20.
    发明申请
    BOOST BYPASS CIRCUITRY IN A MEMORY STORAGE DEVICE 审中-公开

    公开(公告)号：US20200020371A1

    公开(公告)日：2020-01-16

    申请号：US16502596

    申请日：2019-07-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Yen-Huei CHEN

    IPC: G11C7/12 ,  G11C5/14 ,  H03K19/003 ,  G11C7/08 ,  G11C7/10

    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

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