公开(公告)号：US20230317664A1

公开(公告)日：2023-10-05

申请号：US18330616

申请日：2023-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chun Cho ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L23/293 ,  H01L23/3142 ,  H01L23/3135 ,  H01L25/0655 ,  H01L21/56 ,  H01L23/481 ,  H01L24/13 ,  H01L23/5384 ,  H01L2924/37001 ,  H01L2224/2101 ,  H01L2924/35121

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

公开(公告)号：US20230268196A1

公开(公告)日：2023-08-24

申请号：US18308909

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L21/4857 ,  H01L24/13 ,  H01L21/561 ,  H01L21/486 ,  H01L23/49822 ,  H01L21/4853 ,  H01L21/6835 ,  H01L2924/19106 ,  H01L21/568 ,  H01L2224/10122 ,  H01L2221/68331

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

公开(公告)号：US11721603B2

公开(公告)日：2023-08-08

申请号：US17220722

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49861

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

公开(公告)号：US11682647B2

公开(公告)日：2023-06-20

申请号：US16836934

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Shih-Peng Tai ,  Yu-Hsiang Hu ,  I-Chia Chen

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2224/2105

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

公开(公告)号：US11600574B2

公开(公告)日：2023-03-07

申请号：US17121020

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

Abstract: A method includes encapsulating a device die in an encapsulating material, planarizing the device die and the encapsulating material, and forming a first plurality of conductive features electrically coupling to the device die. The step of forming the first plurality of conductive features includes a deposition-and-etching process, which includes depositing a blanket copper-containing layer, forming a patterned photo resist over the blanket copper-containing layer, and etching the blanket copper-containing layer to transfer patterns of the patterned photo resist into the blanket copper-containing layer.

公开(公告)号：US11508633B2

公开(公告)日：2022-11-22

申请号：US16886755

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Tai-Min Chang ,  Chia-Wei Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

公开(公告)号：US11495506B2

公开(公告)日：2022-11-08

申请号：US16835146

申请日：2020-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Tseng ,  Hung-Jui Kuo ,  Ming-Che Ho

IPC: G11C5/06 ,  H01L27/108 ,  H01L21/02 ,  H01L21/56 ,  H01L21/762 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer. The second redistribution structure is disposed over the second integrated circuit structure and the second encapsulation material.

公开(公告)号：US20220336307A1

公开(公告)日：2022-10-20

申请号：US17809924

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co,.Ltd.

Inventor： Hung-Jui Kuo ,  Tai-Min Chang ,  Hui-Jung Tsai ,  De-Yuan Lu ,  Ming-Tan Lee

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48

Abstract: A package includes a device die, an encapsulant encapsulating the device die therein, a first plurality of through-vias penetrating through the encapsulant, a second plurality of through-vias penetrating through the encapsulant, and redistribution lines over and electrically coupling to the first plurality of through-vias. The first plurality of through-vias include an array. The second plurality of through-vias are outside of the first array, and the second plurality of through-vias are larger than the first plurality of through-vias.

公开(公告)号：US11450603B2

公开(公告)日：2022-09-20

申请号：US16876086

申请日：2020-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L21/3105

Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

公开(公告)号：US20210391304A1

公开(公告)日：2021-12-16

申请号：US17099953

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.