公开(公告)号：US12100751B2

公开(公告)日：2024-09-24

申请号：US18123596

申请日：2023-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02274 ,  H01L21/823431 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

公开(公告)号：US20230326967A1

公开(公告)日：2023-10-12

申请号：US18333981

申请日：2023-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L21/2654 ,  H01L27/0924

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US10957545B2

公开(公告)日：2021-03-23

申请号：US16206788

申请日：2018-11-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jia-Ming Lin ,  Shiu-Ko Jangjian ,  Chun-Che Lin

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L29/66 ,  H01L29/49 ,  H01L29/51

Abstract: A method includes etching a dummy gate to form an opening. A gate dielectric layer is deposited in the opening. A blocking layer is deposited over the gate dielectric layer, wherein the blocking layer has a bottom portion over a bottom of the opening and a sidewall portion over a sidewall of the opening. An adhesive layer is deposited over the bottom portion of the blocking layer. A metal layer is deposited over the adhesive layer, wherein the metal layer is in contact with the sidewall portion of the blocking layer.

公开(公告)号：US09991154B2

公开(公告)日：2018-06-05

申请号：US15054113

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ken Lin ,  Jia-Ming Lin ,  Hsien-Che Teng ,  Yung-Chou Shih ,  Kun-Dian She ,  Lichia Yang ,  Yun-Wen Chu

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

公开(公告)号：US20170250106A1

公开(公告)日：2017-08-31

申请号：US15054113

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Ken Lin ,  Jia-Ming Lin ,  Hsien-Che Teng ,  Yung-Chou Shih ,  Kun-Dian She ,  Lichia Yang ,  Yun-Wen Chu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02337 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a shallow trench isolation (STI) structure comprises the following steps. A silane-base precursor having a volumetric flowrate of 500 to 750 sccm and a nitrogen-base precursor having a volumetric flowrate of 300 to 600 sccm are introduced and mixed under a first pressure ranging from 0.5 to 1.5 torr at a first temperature ranging from 30 to 105 centigrade to deposit a flowable dielectric layer in a trench of a substrate. Then, ozone gas and oxygen gas are introduced and mixed under a second pressure ranging from 300 to 650 torr at a second temperature ranging from 50 to 250 centigrade to treat the flowable dielectric layer, wherein a volumetric flowrate ratio of ozone gas and oxygen gas ranges from 1:1 to 3:1. A method for fabricating a FinFET is provided.

公开(公告)号：US09691766B1

公开(公告)日：2017-06-27

申请号：US15088117

申请日：2016-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Ming Lin ,  Chun Che Lin ,  Shiu-Ko JangJian ,  Wei Ken Lin ,  Kuang Yao Lo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803

Abstract: A fin field effect transistor (FinFET) including a substrate, a plurality of insulators, and a gate stack is provided. The substrate includes a plurality of trenches and at least one semiconductor fin between the trenches. The insulators are disposed in the trenches and include doped regions distributed therein. The gate stack partially covers the at least one semiconductor fin and the insulators. A method for fabricating the aforesaid FinFET is also discussed.

公开(公告)号：US20250142904A1

公开(公告)日：2025-05-01

申请号：US19002361

申请日：2024-12-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H10D62/10 ,  H01L21/265 ,  H10D84/85

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US20220406598A1

公开(公告)日：2022-12-22

申请号：US17532204

申请日：2021-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Kun-Yu Lee ,  Chi On Chui

IPC: H01L21/02

Abstract: A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

公开(公告)号：US20220238648A1

公开(公告)日：2022-07-28

申请号：US17220335

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Jia-Ming Lin ,  Chi On Chui

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/265

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

公开(公告)号：US20220085187A1

公开(公告)日：2022-03-17

申请号：US17140897

申请日：2021-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Fan ,  Tsung-Han Shen ,  Jia-Ming Lin ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chi On Chui

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/02

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.