公开(公告)号：US20190131421A1

公开(公告)日：2019-05-02

申请号：US15797973

申请日：2017-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku SHEN ,  Jin-Mu YIN ,  Tsung-Chieh HSIAO ,  Chia-Lin CHUANG ,  Li-Zhen YU ,  Dian-Hau CHEN ,  Shih-Wei WANG ,  De-Wei YU ,  Chien-Hao CHEN ,  Bo-Cyuan LU ,  Jr-Hung LI ,  Chi-On CHUI ,  Min-Hsiu HUNG ,  Huang-Yi HUANG ,  Chun-Cheng CHOU ,  Ying-Liang CHUANG ,  Yen-Chun HUANG ,  Chih-Tang PENG ,  Cheng-Po CHAU ,  Yen-Ming CHEN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/78 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

公开(公告)号：US20240258158A1

公开(公告)日：2024-08-01

申请号：US18630814

申请日：2024-04-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Huan-Chieh SU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/7682 ,  H01L21/0259 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.

公开(公告)号：US20240021682A1

公开(公告)日：2024-01-18

申请号：US18353027

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Yu-Ming LIN ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L21/285 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L29/41725 ,  H01L29/66545 ,  H01L29/401 ,  H01L21/0228 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/28556 ,  H01L27/0886 ,  H01L27/0924 ,  H01L21/32137

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US20230268403A1

公开(公告)日：2023-08-24

申请号：US17858861

申请日：2022-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chi CHUANG ,  Li-Zhen YU ,  Huan-Chieh SU ,  Chun-Yuan CHEN ,  Lin-Yu HUANG ,  Chih-Hao WANG

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L29/401 ,  H01L29/66742 ,  H01L29/66439

Abstract: A device includes semiconductor device structure includes a first dielectric layer. A first plurality of nanostructures are disposed on the first dielectric layer, with the first plurality of nanostructures overlying one another. A first source/drain region is disposed laterally adjacent to a first side of the first plurality of nanostructures. A second dielectric layer is on a first side of the first source/drain region. A front side source/drain contact is disposed on a second side of the first source/drain region that is opposite the first side, and a backside source/drain contact is disposed on the first side of the first source/drain region. The backside source/drain contact extends through the second dielectric layer.

公开(公告)号：US20230138012A1

公开(公告)日：2023-05-04

申请号：US17743352

申请日：2022-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan CHEN ,  Huan-Chieh SU ,  Li-Zhen YU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A device includes a substrate and a transistor on the substrate. The transistor includes a channel region that has at least one semiconductor nanostructure, and a gate electrode. A source/drain region is disposed adjacent to a first side of the channel region along a first direction. A hybrid fin structure is disposed adjacent to a second side of the channel region along a second direction that is transverse to the first direction. The hybrid fin structure includes a first hybrid fin dielectric layer and a second hybrid fin dielectric layer. The first and second hybrid fin dielectric layers include silicon, oxygen, carbon and nitrogen and have a different concentration of at least one of silicon oxygen, carbon, or nitrogen from one another.

公开(公告)号：US20220359685A1

公开(公告)日：2022-11-10

申请号：US17814098

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen YU ,  Cheng-Chi CHUANG ,  Chih-Hao WANG ,  Huan-Chieh SU ,  Lin-Yu HUANG

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/78

Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

公开(公告)号：US20220352015A1

公开(公告)日：2022-11-03

申请号：US17477333

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao CHANG ,  Jia-Chuan YOU ,  Li-Zhen YU ,  Lin-Yu HUANG

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device with reduced contact resistance is provided. The semiconductor device includes a substrate having a channel region and a source/drain region, a source/drain contact structure over the source/drain region, a conductive structure over the source/drain contact structure, an interlayer dielectric (ILD) layer surrounding the conductive structure and source/drain contact structure, a dielectric liner between the ILD layer and the conductive structure, and a diffusion barrier between the dielectric liner and the conductive structure.

公开(公告)号：US20220344464A1

公开(公告)日：2022-10-27

申请号：US17238983

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuang CHIU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG ,  Huan-Chieh SU ,  Chun-Yuan CHEN ,  Li-Zhen YU ,  Yu-Ming LIN

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

公开(公告)号：US20220130991A1

公开(公告)日：2022-04-28

申请号：US17081915

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen YU ,  Huan-Chieh SU ,  Shih-Chuan CHIU ,  Lin-Yu HUANG ,  Cheng-Chi CHUANG ,  Chih-Hao WANG

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.

公开(公告)号：US20220037190A1

公开(公告)日：2022-02-03

申请号：US16943996

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu HUANG ,  Li-Zhen YU ,  Chia-Hao CHANG ,  Cheng-Chi CHUANG ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.