公开(公告)号：US20200043795A1

公开(公告)日：2020-02-06

申请号：US16285052

申请日：2019-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/78 ,  H01L23/522 ,  H01L21/768

Abstract: A method includes following steps. A semiconductor fin is formed on a substrate and extends in a first direction. A source/drain region is formed on the semiconductor fin and a first interlayer dielectric (ILD) layer over the source/drain region. A gate stack is formed across the semiconductor fin and extends in a second direction substantially perpendicular to the first direction. A patterned mask having a first opening is formed over the first ILD layer. A protective layer is formed in the first opening using a deposition process having a faster deposition rate in the first direction than in the second direction. After forming the protective layer, the first opening is elongated in the second direction. A second opening is formed in the first ILD layer and under the elongated first opening. A conductive material is formed in the second opening.

公开(公告)号：US20200006085A1

公开(公告)日：2020-01-02

申请号：US16383539

申请日：2019-04-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ya-Wen YEH ,  Yu-Tien SHEN ,  Shih-Chun HUANG ,  Po-Chin CHANG ,  Wei-Liang LIN ,  Yung-Sung YEN ,  Wei-Hao WU ,  Li-Te LIN ,  Pinyen LIN ,  Ru-Gun LIU

IPC: H01L21/3213 ,  H01L21/66

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

公开(公告)号：US20250022802A1

公开(公告)日：2025-01-16

申请号：US18221638

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tzu Pei Chen ,  Sung-Li Wang ,  Shin-Yi Yang ,  Po-Chin Chang ,  Yuting Cheng ,  Chia-Hung Chu ,  Chun-Hung Liao ,  Harry CHIEN ,  Chia-Hao Chang ,  Pinyen LIN

IPC: H01L23/535 ,  H01L21/768

Abstract: An integrated circuit (IC) with conductive structures and a method of fabricating the IC are disclosed. The method includes depositing a first dielectric layer on a semiconductor device, forming a conductive structure in the first dielectric layer, removing a portion of the first dielectric layer to expose a sidewall of the conductive structure, forming a barrier structure surrounding the sidewall of the conductive structure, depositing a conductive layer on the barrier structure, and performing a polishing process on the barrier structure and the conductive layer.

公开(公告)号：US20220384601A1

公开(公告)日：2022-12-01

申请号：US17818918

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hsu-Kai CHANG ,  Jhih-Rong HUANG ,  Yen-Tien TUNG ,  Chia-Hung CHU ,  Shuen-Shin LIANG ,  Tzer-Min SHEN ,  Pinyen LIN ,  Sung-Li WANG

IPC: H01L29/45 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/78

Abstract: A semiconductor device with different configurations of contact structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second gate structures disposed on first and second fin structures, first and second source/drain (S/D) regions disposed on the first and second fin structures, first and second contact structures disposed on the first and second S/D regions, and a dipole layer disposed at an interface between the first nWFM silicide layer and the first S/D region. The first contact structure includes a first nWFM silicide layer disposed on the first S/D region and a first contact plug disposed on the first nWFM silicide layer. The second contact structure includes a pWFM silicide layer disposed on the second S/D region, a second nWFM silicide layer disposed on the pWFM silicide layer, and a second contact plug disposed on the pWFM silicide layer.

公开(公告)号：US20210210614A1

公开(公告)日：2021-07-08

申请号：US17207425

申请日：2021-03-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01J37/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3213

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US20200294851A1

公开(公告)日：2020-09-17

申请号：US16888929

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang SUN ,  Po-Chin CHANG ,  Akira MINEJI ,  Zi-Wei FANG ,  Pinyen LIN

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/532

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

公开(公告)号：US20200098890A1

公开(公告)日：2020-03-26

申请号：US16559369

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3213

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

公开(公告)号：US20190165123A1

公开(公告)日：2019-05-30

申请号：US16158141

申请日：2018-10-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yi-Chen LO ,  Jung-Hao CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L21/3065

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

公开(公告)号：US20250113517A1

公开(公告)日：2025-04-03

申请号：US18477648

申请日：2023-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-An WANG ,  Ding-Kang SHIH ,  Chia-Ling PAI ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method of forming source/drain regions of semiconductor devices is disclosed. The method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a S/D region in the opening. The forming the S/D region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. The exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.

公开(公告)号：US20240274471A1

公开(公告)日：2024-08-15

申请号：US18626229

申请日：2024-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin CHANG ,  Li-Te LIN ,  Pinyen LIN

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/02263 ,  H01L21/3213 ,  H01L21/76802 ,  H01L21/823475 ,  H01L23/5226 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact, and a first conductive via. The gate structure is over the semiconductor substrate. The source/drain region is adjacent the gate structure. The source/drain contact is over the source/drain region. The first conductive via is over the source/drain contact. From a top view, the first conductive via has two opposite first long sides and two opposite first short sides connecting the first long sides, and the first short sides are shorter than the first long sides and more curved than the first long sides. From a cross-sectional view, the first long sides of the first conductive via have bottom segments higher than a top surface of the gate structure.