公开(公告)号：US10658482B2

公开(公告)日：2020-05-19

申请号：US15800474

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Shih-Fen Huang

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

公开(公告)号：US10276596B2

公开(公告)日：2019-04-30

申请号：US14453304

申请日：2014-08-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chih-Wen Albert Yao ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L21/28

Abstract: Some embodiments of the present disclosure relate to deceasing off-state leakage current within a metal-oxide-semiconductor field-effect transistor (MOSFET). The MOSFET includes source and drain regions. The source and drain regions are separated by a channel region. A gate is arranged over the channel region. The gate has a first gate region adjacent to the source region and a second gate region adjacent to the drain region. The first gate region is selectively doped adjacent the source region. The second gate region is undoped or lightly-doped. The undoped or lightly-doped second gate region reduces the electric field between the gate and the drain region, and hence reduces a gate induced drain leakage (GIDL) current between the gate and drain region. The undoped or lightly-doped region of the gate can reduce the GIDL current within the MOSFET by about three orders of magnitude. Other embodiments are also disclosed.

公开(公告)号：US20160181422A1

公开(公告)日：2016-06-23

申请号：US14580636

申请日：2014-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7824 ,  H01L29/0626 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/401 ,  H01L29/402 ,  H01L29/66681

Abstract: An integrated circuit (IC) includes a high-voltage (HV) MOSFET on a substrate. The substrate includes a handle substrate region, an insulating region, and a silicon region. Source region and drain regions, which have a first conductivity type, are disposed in the silicon region and spaced apart from one another. A gate electrode is disposed over an upper region of the silicon region and is arranged between the source and drain regions. A body region, which has a second conductivity type, is arranged under the gate electrode and separates the source and drain regions. A lateral drain extension region, which has the first conductivity type, is disposed in the upper region of the silicon region and extends laterally between the body and drain regions. A breakdown voltage enhancing region, which has the second conductivity type, is disposed in the silicon region under the lateral drain extension region.

Abstract translation: 集成电路（IC）包括在基板上的高压（HV）MOSFET。 基板包括手柄基板区域，绝缘区域和硅区域。 具有第一导电类型的源极区和漏极区被布置在硅区域中并彼此间隔开。 栅电极设置在硅区域的上部区域上并且布置在源区域和漏极区域之间。 具有第二导电类型的体区被布置在栅电极下方并分离源区和漏区。 具有第一导电类型的横向漏极延伸区域设置在硅区域的上部区域中，并且在主体区域和漏极区域之间横向延伸。 具有第二导电类型的击穿电压增强区域设置在侧向漏极延伸区域下方的硅区域中。

公开(公告)号：US09343465B2

公开(公告)日：2016-05-17

申请号：US14472496

申请日：2014-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Ruey-Hsin Liu ,  Chih-Wen Albert Yao ,  Ming-Ta Lei

IPC: H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/28035 ,  H01L21/28273 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7883

Abstract: Some embodiments of the present disclosure are directed to an embedded flash (e-flash) memory device that includes a flash memory cell and a metal-oxide-semiconductor field-effect transistor (MOSFET). The flash memory cell includes a control gate disposed over a floating gate. The MOSFET includes a logic gate disposed over a gate dielectric. The floating gate and a first gate layer of the logic gate are simultaneously formed with a first polysilicon layer. A high temperature oxide (HTO) is then formed over the floating gate with a high temperature process, while the first gate layer protects the gate dielectric from degradation effects due to the high temperature process. A second gate layer of the logic gate is then formed over the first gate layer by a second polysilicon layer. The first and second gate layers collectively form a logic gate of the MOSFET.

Abstract translation: 本公开的一些实施例涉及包括闪存单元和金属氧化物半导体场效应晶体管（MOSFET）的嵌入式闪存（e-flash）存储器件。 闪存单元包括设置在浮动栅极上的控制栅极。 MOSFET包括设置在栅极电介质上的逻辑门。 逻辑门的浮置栅极和第一栅极层同时形成有第一多晶硅层。 然后，通过高温工艺在浮栅上形成高温氧化物（HTO），而第一栅极层由于高温处理而保护栅极电介质免受劣化影响。 然后通过第二多晶硅层在第一栅极层上形成逻辑门的第二栅极层。 第一和第二栅极层共同形成MOSFET的逻辑门。

公开(公告)号：US11508757B2

公开(公告)日：2022-11-22

申请号：US17323016

申请日：2021-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Ruey-Hsin Liu ,  Ming-Ta Lei

IPC: H01L27/12 ,  H01L23/48 ,  H01L29/06 ,  H01L29/10 ,  H01L21/84 ,  H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a semiconductor substrate having a device substrate overlying a handle substrate and an insulator layer disposed between the device substrate and the handle substrate. A gate electrode overlies the device substrate between a drain region and a source region. A conductive via extends through the device substrate and the insulator layer to contact the handle substrate. A first isolation structure is disposed within the device substrate and comprises a first isolation segment disposed laterally between the gate electrode and the conductive via. A contact region is disposed within the device substrate between the first isolation segment and the conductive via. A conductive gate electrode directly overlies the first isolation segment and is electrically coupled to the contact region.

公开(公告)号：US11444169B2

公开(公告)日：2022-09-13

申请号：US16929640

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

公开(公告)号：US20200343195A1

公开(公告)日：2020-10-29

申请号：US16924627

申请日：2020-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L23/552 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L21/762

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

公开(公告)号：US10680100B2

公开(公告)日：2020-06-09

申请号：US16026290

申请日：2018-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chih Su ,  Hsueh-Liang Chou ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/765 ,  H01L29/66 ,  H01L29/40

Abstract: The present disclosure relates to a high voltage transistor device having a field structure that includes at least one conduction unit, and a method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed over a substrate between a source region and a drain region located within the substrate. A dielectric layer laterally extends from over the gate electrode to over a drift region between the gate electrode and the drain region. A field structure is located within the first ILD layer. The field structure includes a conduction unit having a vertically elongated shape and vertically extending from a top surface of the dielectric layer and a top surface of the first ILD layer.

公开(公告)号：US09627551B2

公开(公告)日：2017-04-18

申请号：US14026580

申请日：2013-09-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Chih Chiang ,  Tung-Yang Lin ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC: H01L29/66 ,  H01L29/87

CPC classification number: H01L29/87 ,  H01L29/0607 ,  H01L29/66121

Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

公开(公告)号：US09472665B2

公开(公告)日：2016-10-18

申请号：US14024872

申请日：2013-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chang Cheng ,  Fu-Yu Chu ,  Ruey-Hsin Liu

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/7835 ,  H01L21/28052 ,  H01L21/28105 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66659 ,  H01L29/7833

Abstract: A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.

Abstract translation: 提供了一种新颖的MOS晶体管，其包括源极区，漏极区，沟道区，隔离区，漂移区，栅极介电层，栅电极和场板。 栅电极具有第一部分和第二部分。 第一导电类型的第一部分位于沟道区上方，并且具有等于或大于与沟道区重叠的栅电极的距离的宽度。 第二部分是未掺杂的并且位于隔离区上方。 因此，MOS晶体管允许更高的工艺自由度节省生产成本，并提高可靠性。