公开(公告)号：US20210327528A1

公开(公告)日：2021-10-21

申请号：US16851107

申请日：2020-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mao-Ruei Li ,  Fan-Ming Kuo ,  Wei-Li Chen

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/46 ,  G11C29/12 ,  G11C29/56

Abstract: A data verifying method, a chip, and a verifying apparatus are provided. In the method, an encoder is provided for at least one processing circuit of a chip. One or more transmitting data of a to-be-test circuit of the processing circuit is encoded through the encoder to generate one or more parity data. The transmitting data is a computing result generated by the to-be-test circuit. The parity data is transmitted without the transmitting data. The parity data is used for data verification of the transmitting data.

公开(公告)号：US09350324B2

公开(公告)日：2016-05-24

申请号：US13727850

申请日：2012-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsiung Lee ,  Shi-Hung Wang ,  Kuang-Kai Yen ,  Wei-Li Chen ,  Yung-Hsu Chuang ,  Shih-Hung Lan ,  Fan-ming Kuo ,  Chewn-Pu Jou ,  Fu-Lung Hsueh

IPC: H03K3/00 ,  H03K3/012 ,  H03K3/3562 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/356043 ,  H03K3/3562

Abstract: The present disclosure relates to a device and method to reduce the dynamic/static power consumption of an MCML logic device. In order to retain register contents during power off mode, an MCML retention latch and flip-flop are disclosed. Retention Latch circuits in MCML architecture are used to retain critical register contents during power off mode, wherein combination logic including clock buffers on the clock tree paths are powered off to reduce dynamic/static power consumption. The MCML retention flip-flop comprises a master latch and a slave latch, wherein a power switch is added to the master latch to power the master latch off during power off mode. The slave latch includes pull-down circuits that remain active to enable the slave latch to retain data at a proper voltage level during power off mode. Other devices and methods are also disclosed.

Abstract translation: 本公开涉及一种减少MCML逻辑器件的动态/静态功耗的装置和方法。 为了在断电模式下保持寄存器内容，公开了一种MCML保持锁存器和触发器。 保留MCML架构中的锁存电路用于在断电模式下保留关键寄存器内容，其中包括时钟树路径上的时钟缓冲器的组合逻辑被关闭以减少动态/静态功耗。 MCML保持触发器包括主锁存器和从锁存器，其中在断电模式期间将电源开关加到主锁存器以为主锁存器供电。 从锁存器包括保持有效的下拉电路，以使从锁存器在断电模式期间将数据保持在适当的电压电平。 还公开了其它装置和方法。

公开(公告)号：US20150243763A1

公开(公告)日：2015-08-27

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。