公开(公告)号：US09899441B1

公开(公告)日：2018-02-20

申请号：US15337224

申请日：2016-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Lung Wu ,  Tung-I Lin ,  Yeur-Luen Tu

IPC: H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14689 ,  H01L27/14698

Abstract: A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.

公开(公告)号：US20150243763A1

公开(公告)日：2015-08-27

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US20160111511A1

公开(公告)日：2016-04-21

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/423 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09245974B2

公开(公告)日：2016-01-26

申请号：US14187850

申请日：2014-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/311 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a method of generating a transistor device having an epitaxial layer disposed over a recessed active region. The epitaxial layer improves transistor device performance. In some embodiments, the method is performed by providing a semiconductor substrate. An epitaxial growth is performed to form an epitaxial layer onto the semiconductor substrate. An electrically insulating layer is then formed onto the epitaxial layer, and a gate structure is formed onto the electrically insulating layer. By forming the epitaxial layer over the semiconductor substrate the surface roughness of the semiconductor substrate is improved, thereby improving transistor device performance.

Abstract translation: 本公开涉及一种生成具有设置在凹入的有源区上的外延层的晶体管器件的方法。 外延层改善晶体管器件的性能。 在一些实施例中，通过提供半导体衬底来执行该方法。 进行外延生长以在半导体衬底上形成外延层。 然后在外延层上形成电绝缘层，并且在电绝缘层上形成栅极结构。 通过在半导体衬底上形成外延层，改善了半导体衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09099324B2

公开(公告)日：2015-08-04

申请号：US14062838

申请日：2013-10-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

Abstract translation: 半导体器件包括半导体衬底和沟槽隔离。 沟槽隔离位于半导体衬底中，并且包括外延层和电介质材料。 外延层位于半导体的沟槽中并由其周边封闭，其中通过进行蚀刻和外延工艺形成外延层。 蚀刻和外延工艺包括蚀刻沟槽的侧壁的一部分和沟槽的底表面的一部分，并且形成与侧壁的剩余部分和底表面的剩余部分共形的外延层。 电介质材料由外延层周边封闭。

公开(公告)号：US09634096B2

公开(公告)日：2017-04-25

申请号：US14755990

申请日：2015-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/70 ,  H01L29/167 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

公开(公告)号：US09595589B2

公开(公告)日：2017-03-14

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L27/146 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。