公开(公告)号：US20140212627A1

公开(公告)日：2014-07-31

申请号：US13751540

申请日：2013-01-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jay Lai ,  Ying-Hao Kuo ,  Hai-Ching Chen ,  Tien-I Bao

IPC: B05D5/06

CPC classification number: G02B6/122 ,  B05D5/06 ,  G02B6/425 ,  G02B6/4298 ,  G02B2006/12102 ,  G02B2006/12173 ,  G03F7/0002 ,  Y10T428/24612

Abstract: Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure.

Abstract translation: 一些实施例涉及加工工件的方法。 工件包括具有第一润湿性系数的第一表面区域和具有与第一润湿性系数不同的第二润湿性系数的第二表面区域。 对应于光学结构的液体被分配在工件的第一和第二表面区域上，其中由于第一和第二润湿性系数之间的差异，液体自对准到第二表面区域。 自对准液体被硬化以形成光学结构。

公开(公告)号：US11658044B2

公开(公告)日：2023-05-23

申请号：US17205146

申请日：2021-03-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/4871 ,  H01L21/4878 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/3737 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/83101 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/2919 ,  H01L2924/00014 ,  H01L2224/83101 ,  H01L2924/00014

Abstract: A semiconductor package includes a wafer and at least one chip attached on first portions of an upper surface of the wafer. Further, the semiconductor package includes an insulating barrier layer, a thermally conductive layer, and a heat sink. The insulating barrier layer is arranged over the at least one chip attached on first portions of an upper surface of the wafer. The thermally conductive layer is arranged over the insulating barrier layer and at least partially encapsulates the at least one chip. The heat sink is arranged over the thermally conductive layer.

公开(公告)号：US11088058B2

公开(公告)日：2021-08-10

申请号：US16600752

申请日：2019-10-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/373 ,  H01L23/498 ,  H01L23/433 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56

Abstract: Some embodiments relate to a semiconductor package. The package includes a substrate having an upper surface and a lower surface. A first chip is disposed over a first portion of the upper surface of the substrate. A second chip is disposed over a second portion of the upper surface of the substrate. A first plurality of carbon nano material pillars are disposed over an uppermost surface of the first chip, and a second plurality of carbon nano material pillars are disposed over an uppermost surface of the second chip. A molding compound is disposed above the substrate, and encapsulates the first chip, the first plurality of carbon nano material pillars, the second chip, and the second plurality of carbon nano material pillars.

公开(公告)号：US10983278B2

公开(公告)日：2021-04-20

申请号：US16141621

申请日：2018-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kai-Fang Cheng ,  Hai-Ching Chen ,  Tien-I Bao

IPC: G02B6/132 ,  H01L21/56 ,  H01L29/06 ,  H01L23/31 ,  G02B6/138 ,  G02B6/122 ,  G02B6/136 ,  H01L21/48 ,  G02B6/12

Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.

公开(公告)号：US10861817B2

公开(公告)日：2020-12-08

申请号：US16666708

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/42 ,  H01L23/00 ,  H01L23/373 ,  H01L21/56 ,  H01L23/31 ,  H01L23/433

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.

公开(公告)号：US20200066671A1

公开(公告)日：2020-02-27

申请号：US16666708

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/373 ,  H01L23/42 ,  H01L21/56

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip attached to a first substrate and a thermal conductivity layer attached to the first chip. A molding compound encapsulates the chip and the thermal conductivity layer. Electrical connectors are arranged between the first substrate and a board. The molding compound covers upper surfaces of the thermal conductivity layer facing away from the electrical connectors.

公开(公告)号：US20180138056A1

公开(公告)日：2018-05-17

申请号：US15855305

申请日：2017-12-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/56 ,  H01L23/538 ,  H01L21/48 ,  H01L21/50 ,  H01L31/09 ,  H01L31/0232 ,  H01L27/146 ,  H01L25/00 ,  H01L25/16 ,  H01L23/00 ,  H01L21/311 ,  H01L23/48 ,  H01L23/31 ,  H01L23/29 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to a package for holding a plurality of integrated circuits. The package includes a first conductive pad over a first chip and a second conductive pad over a second chip. A molding structure surrounds the first chip and the second chip. A first passivation layer is over the first chip and the second chip, and a conductive structure is over the first passivation layer. The conductive structure is coupled to the first conductive pad. A second passivation layer is over the conductive structure. The first passivation layer and the second passivation layer have sidewalls defining an aperture that is directly over an optical element within the second chip and that extends through the first passivation layer and the second passivation layer.

公开(公告)号：US20160343697A1

公开(公告)日：2016-11-24

申请号：US15223609

申请日：2016-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wan-Yu Lee ,  Chun-Hao Tseng ,  Jui Hsieh Lai ,  Tien-Yu Huang ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L25/00 ,  H01L23/31 ,  H01L23/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/538 ,  H01L21/683 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L21/31111 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/538 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/82 ,  H01L25/167 ,  H01L25/50 ,  H01L27/14618 ,  H01L31/0232 ,  H01L31/09 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00

Abstract: A package for holding a plurality of heterogeneous integrated circuits includes a first chip having a first conductive pad and a first substrate including a first semiconductor, and a second chip having a second conductive pad and a second substrate including a second semiconductor. The second semiconductor is different from the first semiconductor. The package also includes a molding structure in which the first chip and the second chip are embedded, a conductive structure over the first chip and conductively coupled to the first conductive pad and over the second chip and conductively coupled to the second conductive pad, and a passivation layer over the conductive structure. The passivation layer comprises an opening defined therein which exposes a portion of the second chip.

公开(公告)号：US20210104485A1

公开(公告)日：2021-04-08

申请号：US17104588

申请日：2020-11-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L23/00 ,  H01L23/42 ,  H01L23/373 ,  H01L21/56

Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes a first chip and a second chip attached to a substrate. A thermal conductivity layer is attached to the first chip. A molding compound laterally surrounds the first chip, the second chip, and the thermal conductivity layer. The second chip extends from the substrate to an imaginary horizontally extending line that extends along a horizontally extending surface of the thermal conductivity layer facing away from the substrate. The imaginary horizontally extending line is parallel to the horizontally extending surface.

公开(公告)号：US10957559B2

公开(公告)日：2021-03-23

申请号：US16575698

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hao Tseng ,  Ying-Hao Kuo ,  Kuo-Chung Yee

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/36 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.