公开(公告)号：US11721603B2

公开(公告)日：2023-08-08

申请号：US17220722

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L23/3192 ,  H01L23/49822 ,  H01L23/49861

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

公开(公告)号：US20230223357A1

公开(公告)日：2023-07-13

申请号：US17752272

申请日：2022-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Che Chiang ,  Chien-Hsun Chen ,  Tuan-Yu Hung ,  Hsin-Yu Pan ,  Wei-Kang Hsieh ,  Tsung-Hsien Chiang ,  Chao-Hsien Huang ,  Tzu-Sung Huang ,  Ming Hung Tseng ,  Wei-Chih Chen ,  Ban-Li Wu ,  Hao-Yi Tsai ,  Yu-Hsiang Hu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L25/105 ,  H01L24/20 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L24/19 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2224/214 ,  H01L2221/68359 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.

公开(公告)号：US11682647B2

公开(公告)日：2023-06-20

申请号：US16836934

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Shih-Peng Tai ,  Yu-Hsiang Hu ,  I-Chia Chen

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/19 ,  H01L2224/2101 ,  H01L2224/2105

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

公开(公告)号：US11450603B2

公开(公告)日：2022-09-20

申请号：US16876086

申请日：2020-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sih-Hao Liao ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/538 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L21/3105

Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.

公开(公告)号：US20210391304A1

公开(公告)日：2021-12-16

申请号：US17099953

申请日：2020-11-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device having a redistribution structure and a method of forming the same are provided. A semiconductor device includes a semiconductor structure, a redistribution structure over and electrically coupled the semiconductor structure, and a connector over and electrically coupled to the redistribution structure. The redistribution structure includes a base via and stacked vias electrically interposed between the base via and the connector. The stacked vias are laterally spaced apart from the base via.

公开(公告)号：US20210217709A1

公开(公告)日：2021-07-15

申请号：US17215297

申请日：2021-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L23/58 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/485 ,  H01L23/00 ,  H01L21/683

Abstract: A method includes encapsulating a package component in an encapsulating material, with the encapsulating material including a portion directly over the package component. The portion of the encapsulating material is patterned to form an opening revealing a conductive feature in the package component. A redistribution line extends into the opening to contact the conductive feature. An electrical connector is formed over and electrically coupling to the conductive feature.

公开(公告)号：US10998202B2

公开(公告)日：2021-05-04

申请号：US16527015

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/367 ,  H01L23/538 ,  H01L23/544 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31

Abstract: A semiconductor package includes a die and an encapsulant. The die has an active surface and an opposite backside surface. The encapsulant wraps around the die and has a recess reaching the backside surface. A span of the recess differs from a span of the backside surface and a span of the encapsulant. A manufacturing method includes at least the following steps. A blanket die attach film is spin-coated. A light exposure process is performed to the blanket die attach film. Blanket die attach film is developed to form a patterned die adhesive. A die is disposed over the patterned die adhesive with a backside surface closer to the patterned die adhesive. The patterned die adhesive is cured to affix the die. The die and the cured die adhesive are encapsulated in an encapsulant. The cured die adhesive is removed.

公开(公告)号：US10790212B2

公开(公告)日：2020-09-29

申请号：US16675227

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3105

Abstract: A method of manufacturing a package structure includes the following processes. An adhesive layer is formed on a carrier. A die is attached to the carrier through the adhesive layer. A protection layer is formed to at least cover a sidewall and a portion of a top surface of the adhesive layer on an edge of the carrier. An encapsulant is formed over the carrier to laterally encapsulate the die. A redistribution layer (RDL) structure is formed on the die and the encapsulant. A connector is formed to electrically connect to the die through the RDL structure. The carrier is released.

公开(公告)号：US10763206B2

公开(公告)日：2020-09-01

申请号：US15879457

申请日：2018-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/768 ,  H01L23/00 ,  H01L21/66 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498

Abstract: A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

公开(公告)号：US10685896B2

公开(公告)日：2020-06-16

申请号：US15486306

申请日：2017-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zi-Jheng Liu ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/11 ,  H01L23/544 ,  H01L25/00 ,  H01L21/683 ,  H01L21/56 ,  H01L25/10 ,  H01L23/538

Abstract: An integrated circuit package including an integrated circuit component, a patterned dielectric liner, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit component includes an active surface and conductive vias distributed on the active surface. The patterned dielectric liner conformally covers the active surface of the integrated circuit component and sidewalls of the conductive vias. The insulating encapsulation encapsulates sidewalls of the integrated circuit component and covers the patterned dielectric liner. The insulating encapsulation includes a planar top surface. The planar top surface of the insulating encapsulation is substantially coplanar with top surfaces of the conductive vias. The insulating encapsulation and the conductive vias are spaced apart by the patterned dielectric liner. The redistribution circuit structure is disposed on the planar top surface of the insulating encapsulation, the top surfaces of the conductive vias and the patterned dielectric liner. The redistribution circuit structure is electrically connected to the conductive vias.