公开(公告)号：US20170358569A1

公开(公告)日：2017-12-14

申请号：US15670356

申请日：2017-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie LIN ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/28 ,  H02H9/04 ,  H01L29/10 ,  H01L29/66 ,  H01L23/60 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/0266 ,  H01L21/28123 ,  H01L21/823431 ,  H01L21/823437 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0292 ,  H01L27/0886 ,  H01L29/1095 ,  H01L29/66545 ,  H02H9/046

Abstract: An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first gate device and a second gate device. The integrated circuit device includes at least one dummy gate between the two epitaxially grown active regions and between the first gate device and the second gate device, wherein each active region is substantially uniform in length. The first gate device and the second device are formed over a first well having a first conductivity type and the dummy gate is formed over a second well having a second conductivity type.

公开(公告)号：US11961834B2

公开(公告)日：2024-04-16

申请号：US17699471

申请日：2022-03-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Li-Wei Chu ,  Ming-Fu Tsai ,  Jam-Wem Lee ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/86 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L29/08 ,  H01L29/10 ,  H01L29/747 ,  H01L29/861

CPC classification number: H01L27/0262 ,  H01L27/0207 ,  H01L27/0255 ,  H01L29/87 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0248 ,  H01L27/0652 ,  H01L27/0658 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/747 ,  H01L29/8611 ,  H01L2924/13034 ,  H01L2924/13035

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US20190131293A1

公开(公告)日：2019-05-02

申请号：US16219747

申请日：2018-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L21/28 ,  H01L23/60 ,  H01L21/8234 ,  H01L29/10 ,  H01L27/088 ,  H02H9/04 ,  H01L29/66

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US12094871B2

公开(公告)日：2024-09-17

申请号：US17706521

申请日：2022-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0285 ,  H01L27/0255 ,  H01L27/0274 ,  H02H9/046

Abstract: An integrated circuit includes a diode string, a first transistor, a second transistor, and a third transistor. The diode string is coupled between a first reference voltage pin and an input/output (I/O) pad. A first terminal of the second transistor is coupled to a first node, and a gate terminal of the second transistor is coupled to a second reference voltage pin. In response to a voltage at the first terminal of the second transistor being higher than a voltage at the gate terminal of the second transistor, the second transistor is configured to turn on the third transistor, and the third transistor is configured to transmit a voltage received from the first reference voltage pin to a gate terminal of the first transistor.

公开(公告)号：US11710962B2

公开(公告)日：2023-07-25

申请号：US17827776

申请日：2022-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su ,  Chia-Wei Hsu ,  Ming-Fu Tsai ,  Shu-Yu Su ,  Li-Wei Chu ,  Jam-Wem Lee ,  Chia-Jung Chang ,  Hsiang-Hui Cheng

IPC: H02H9/04 ,  G01R31/00 ,  H02H1/00

CPC classification number: H02H9/046 ,  G01R31/001 ,  H02H1/0007

Abstract: A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

公开(公告)号：US11676959B2

公开(公告)日：2023-06-13

申请号：US17836899

申请日：2022-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fu Tsai ,  Tzu-Heng Chang ,  Yu-Ti Su ,  Kai-Ping Huang

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0285 ,  H01L27/0296 ,  H02H9/046

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

公开(公告)号：US11289472B2

公开(公告)日：2022-03-29

申请号：US16943882

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Yu-Ti Su

IPC: H01L27/02 ,  H02H9/04

Abstract: An integrated circuit includes an input/output (I/O) pad, an electrostatic discharge (ESD) primary circuit and a bias voltage generator. The electrostatic discharge primary circuit includes a first transistor. A first terminal of the first transistor is coupled to the I/O pad. The bias voltage generator is configured to provide a gate bias signal to the gate terminal of the first transistor. The bias voltage generator provides the gate bias signal at a first voltage level in response to that an ESD event occurs on the I/O pad. The bias voltage generator provides the gate bias signal at a second voltage level in response to that no ESD event occurs on the I/O pad. The first voltage level is lower than the second voltage level.

公开(公告)号：US11282831B2

公开(公告)日：2022-03-22

申请号：US16575091

申请日：2019-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Lin Peng ,  Li-Wei Chu ,  Ming-Fu Tsai ,  Jam-Wem Lee ,  Yu-Ti Su

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/87 ,  H01L29/86 ,  H01L29/08 ,  H01L29/10 ,  H01L29/74 ,  H01L23/60 ,  H01L23/62 ,  H01L29/747 ,  H01L29/861

Abstract: A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

公开(公告)号：US20210082907A1

公开(公告)日：2021-03-18

申请号：US17107694

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wun-Jie Lin ,  Han-Jen Yang ,  Yu-Ti Su

IPC: H01L27/02 ,  H02H9/04 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/66 ,  H01L23/60 ,  H01L21/28

Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.

公开(公告)号：US10804267B2

公开(公告)日：2020-10-13

申请号：US15881215

申请日：2018-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien Yao Huang ,  Yu-Ti Su

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/74 ,  H01L21/8238 ,  H01L21/761 ,  H01L29/78

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.