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    CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME
    11.
    发明申请
    CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME 有权

    公开(公告)号：US20220123115A1

    公开(公告)日：2022-04-21

    申请号：US17193626

    申请日：2021-03-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Pei-Yu Chou ,  Jr-Hung Li ,  Tze-Liang Lee

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/40 ,  H01L23/535

    Abstract: A semiconductor device a method of forming the same are provided. A semiconductor device includes a gate stack over a substrate. A first dielectric layer is over the gate stack. The first dielectric layer includes a first material. A second dielectric layer is over the first dielectric layer. The second dielectric layer includes a second material different from the first material. A first conductive feature is adjacent the gate stack. A second conductive feature is over and in physical contact with a topmost surface of the first conductive feature. A bottommost surface of the second conductive feature is in physical contact with a topmost surface of the second dielectric layer.

    FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    12.
    发明申请
    FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20210091191A1

    公开(公告)日：2021-03-25

    申请号：US16805841

    申请日：2020-03-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tsai-Jung Ho ,  Jr-Hung Li ,  Tze-Liang Lee ,  Pei-Yu Chou ,  Chi-Ta Lee

    IPC: H01L29/417 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L29/78

    Abstract: A field effect transistor includes a semiconductor substrate, source and drain regions, lower source and drain contacts, a metal gate, a first interlayer dielectric layer, a capping layer, and an etch stop layer. The source and drain regions are disposed on the semiconductor substrate. The lower source and drain contacts are disposed on the source and drain regions. The metal gate is disposed in between the lower source and drain contacts. The first interlayer dielectric layer encircles the metal gate and the lower source and drain contacts. The capping layer is disposed on the metal gate. The etch stop layer extends on the first interlayer dielectric layer. An etching selectivity for the etch stop layer over the capping layer is greater than 10.

    Low-k gate spacer and formation thereof
    13.
    发明授权
    Low-k gate spacer and formation thereof 有权

    公开(公告)号：US10483168B2

    公开(公告)日：2019-11-19

    申请号：US15833912

    申请日：2017-12-06

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

    Low-K Gate Spacer and Formation Thereof
    15.
    发明申请
    Low-K Gate Spacer and Formation Thereof 审中-公开

    公开(公告)号：US20190148239A1

    公开(公告)日：2019-05-16

    申请号：US16203814

    申请日：2018-11-29

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

    IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423

    Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.

    Dielectric Layers for Semiconductor Devices and Methods of Forming the Same
    18.
    发明公开
    Dielectric Layers for Semiconductor Devices and Methods of Forming the Same 审中-公开

    公开(公告)号：US20230282750A1

    公开(公告)日：2023-09-07

    申请号：US17841493

    申请日：2022-06-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Lien Huang ,  Tze-Liang Lee ,  Jr-Hung Li ,  Chi-Hao Chang ,  Hao-Yu Chang ,  Pei-Yu Chou

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7851 ,  H01L29/66795

    Abstract: Methods of forming improved dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a transistor structure on a semiconductor substrate; a first dielectric layer on the transistor structure; a second dielectric layer on the first dielectric layer, the second dielectric layer having a nitrogen concentration greater than a nitrogen concentration of the first dielectric layer; a first conductive structure extending through the second dielectric layer and the first dielectric layer, the first conductive structure being electrically coupled to a first source/drain region of the transistor structure, a top surface of the first conductive structure being level with a top surface of the second dielectric layer; and a second conductive structure physically and electrically coupled to the first conductive structure, a bottom surface of the second conductive structure being a first distance below the top surface of the second dielectric layer.

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