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    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT
    13.
    发明申请
    STATIC RANDOM ACCESS MEMORY WITH WRITE ASSIST CIRCUIT 有权

    公开(公告)号：US20220383947A1

    公开(公告)日：2022-12-01

    申请号：US17818386

    申请日：2022-08-09

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hidehiro FUJIWARA ,  Chih-Yu LIN ,  Sahil Preet Singh ,  Hsien-Yu PAN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: G11C11/419 ,  G11C11/412

    Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT
    16.
    发明申请
    METHOD AND APPARATUS FOR READ ASSIST TO COMPENSATE FOR WEAK BIT 审中-公开
    用于读取辅助以补偿弱位的方法和装置

    公开(公告)号：US20150131394A1

    公开(公告)日：2015-05-14

    申请号：US14603393

    申请日：2015-01-23

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung CHANG ,  Cheng Hung LEE ,  Chung-Cheng CHOU ,  Hung-Jen LIAO ,  Bin-Hau LO

    IPC: G11C7/12

    CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C11/412 ,  G11C11/419

    Abstract: A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold. The compensation circuit is configured to pull down the voltage of the bit line if the detection signal indicates that the voltage of the bit line is below the predetermined threshold.

    Abstract translation: 记忆辅助装置包括检测电路和补偿电路。 检测电路被配置为提供一个检测信号，该检测信号指示被配置为对存储在存储位单元中的数据位提供读取访问的位线是否具有低于预定阈值的电压。 如果检测信号指示位线的电压低于预定阈值，则补偿电路被配置为下拉位线的电压。

    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES
    17.
    发明申请
    LAYOUT SCHEME AND METHOD FOR FORMING DEVICE CELLS IN SEMICONDUCTOR DEVICES 审中-公开
    用于在半导体器件中形成器件电池的布局方案和方法

    公开(公告)号：US20150118803A1

    公开(公告)日：2015-04-30

    申请号：US14589009

    申请日：2015-01-05

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hsien-Yu PAN ,  Jung-Hsuan CHEN ,  Shao-Yu CHOU ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: H01L27/11 ,  H01L21/768 ,  H01L27/02

    CPC classification number: H01L27/1116 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11 ,  H01L2027/11887

    Abstract: A method and layout for forming word line decoder devices and other devices having word line decoder cells provides for forming metal interconnect layers using non-DPL photolithography operations and provides for stitching distally disposed transistors using a lower or intermediate metal layer or a subjacent conductive material. The transistors may be disposed in or adjacent longitudinally arranged word line decoder or other cells and the conductive coupling using the metal or conductive material lowers gate resistance between transistors and avoids RC signal delays.

    Abstract translation: 用于形成字线解码器装置和具有字线解码器单元的其它装置的方法和布局提供了使用非DPL光刻操作形成金属互连层，并且使用下部或中间金属层或下部导电材料提供了用于缝合的远端布置的晶体管。 晶体管可以设置在纵向布置的字线解码器或其他单元中或其附近，并且使用金属或导电材料的导电耦合降低晶体管之间的栅极电阻并避免RC信号延迟。

    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
    18.
    发明申请
    SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS 有权

    公开(公告)号：US20250159857A1

    公开(公告)日：2025-05-15

    申请号：US19024672

    申请日：2025-01-16

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Hidehiro FUJIWARA ,  Wei-Min CHAN ,  Chih-Yu LIN ,  Yen-Huei CHEN ,  Hung-Jen LIAO

    IPC: H10B10/00 ,  H01L21/321 ,  H01L21/768 ,  H01L23/528 ,  H10D89/10

    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.

    MEMORY DEVICES WITH STRAP CELLS
    20.
    发明申请
    MEMORY DEVICES WITH STRAP CELLS 有权
    具有条纹细胞的记忆装置

    公开(公告)号：US20170076755A1

    公开(公告)日：2017-03-16

    申请号：US15153687

    申请日：2016-05-12

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jonathan Tsung-Yung CHANG ,  Cheng-Hung LEE ,  Chi-Ting CHENG ,  Hung-Jen LIAO ,  Jhon-Jhy LIAW ,  Yen-Huei CHEN

    IPC: G11C5/02 ,  G11C7/22 ,  G11C7/10 ,  G11C5/14

    CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C7/1069 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417

    Abstract: A device includes a memory array, a first data line, and a second data line. The memory array includes a first strap cell, a first sub-bank, and a second sub-bank, in which the first strap cell is disposed between the first sub-bank and the second sub-bank. The first data line has a first portion and a second portion, in which the first portion of the first data line is disconnected from the second portion of the first data line, and the second portion of the first data line is configured to couple the first sub-bank to a first input/output (I/O) circuit. The second data line and the first portion of the first data line are configured to couple the second sub-bank to the first I/O circuit.

    Abstract translation: 一种设备包括存储器阵列，第一数据线和第二数据线。 存储器阵列包括第一带单元，第一子库和第二子库，其中第一带单元设置在第一子库和第二子库之间。 第一数据线具有第一部分和第二部分，其中第一数据线的第一部分与第一数据线的第二部分断开，并且第一数据线的第二部分被配置为将第一数据线的第一部分耦合第一数据线 子行到第一个输入/输出（I / O）电路。 第二数据线和第一数据线的第一部分被配置为将第二子组耦合到第一I / O电路。

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