公开(公告)号：US08436365B2

公开(公告)日：2013-05-07

申请号：US13031280

申请日：2011-02-21

申请人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo Yamamoto ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/16 ,  H01L29/47 ,  H01L29/872

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US20110204383A1

公开(公告)日：2011-08-25

申请号：US13031280

申请日：2011-02-21

申请人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

发明人： Takeo YAMAMOTO ,  Takeshi Endo ,  Jun Morimoto ,  Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Takashi Katsuno ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/24 ,  H01L21/329 ,  B82Y99/00 ,  B82Y40/00

CPC分类号： H01L29/47 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/6606 ,  H01L29/872

摘要： A SiC semiconductor device having a Schottky barrier diode includes: a substrate made of SiC and having a first conductive type, wherein the substrate includes a main surface and a rear surface; a drift layer made of SiC and having the first conductive type, wherein the drift layer is disposed on the main surface of the substrate and has an impurity concentration lower than the substrate; a Schottky electrode disposed on the drift layer and has a Schottky contact with a surface of the drift layer; and an ohmic electrode disposed on the rear surface of the substrate. The Schottky electrode directly contacts the drift layer in such a manner that a lattice of the Schottky electrode is matched with a lattice of the drift layer.

摘要翻译： 具有肖特基势垒二极管的SiC半导体器件包括：由SiC制成并具有第一导电类型的衬底，其中所述衬底包括主表面和后表面; 由SiC制成并具有第一导电类型的漂移层，其中所述漂移层设置在所述衬底的主表面上并且具有低于所述衬底的杂质浓度; 肖特基电极，设置在漂移层上并与漂移层的表面具有肖特基接触; 以及设置在基板的后表面上的欧姆电极。 肖特基电极以使得肖特基电极的晶格与漂移层的晶格匹配的方式直接接触漂移层。

公开(公告)号：US10020390B2

公开(公告)日：2018-07-10

申请号：US15107313

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L21/265

CPC分类号： H01L29/7811 ,  H01L21/047 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/408 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

公开(公告)号：US09780205B2

公开(公告)日：2017-10-03

申请号：US15104332

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L21/04

CPC分类号： H01L29/7811 ,  H01L21/046 ,  H01L21/761 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

摘要： A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

公开(公告)号：US08748975B2

公开(公告)日：2014-06-10

申请号：US13712343

申请日：2012-12-12

申请人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

发明人： Hirokazu Fujiwara ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Toshimasa Yamamoto ,  Yuichi Takeuchi

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/26506 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7827

摘要： A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

摘要翻译： 提供了具有半导体衬底的开关元件。 沟槽栅电极形成在半导体衬底的上表面中。 在与半导体衬底中的栅极绝缘膜接触的区域中形成n型第一半导体区域，p型第二半导体区域和n型第三半导体区域。 在第二半导体区域下方的位置处，形成连接到第二半导体区域的p型第四半导体区域，并且经由第三半导体区域与栅极绝缘膜相对并且含有硼。 在第三半导体区域的至少一部分中，形成具有比在半导体衬底的下表面露出的半导体区域更高的碳浓度的高浓度含碳区域，位于第四半导体区域 以及与第四半导体区域接触的栅极绝缘膜。

公开(公告)号：US09853141B2

公开(公告)日：2017-12-26

申请号：US15107132

申请日：2014-08-04

申请人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

发明人： Jun Saito ,  Hirokazu Fujiwara ,  Tomoharu Ikeda ,  Yukihiko Watanabe ,  Toshimasa Yamamoto

IPC分类号： H01L29/15 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/167 ,  H01L29/739 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L21/76237 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/105 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/7395 ,  H01L29/7811

摘要： Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.

公开(公告)号：US09136372B2

公开(公告)日：2015-09-15

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

公开(公告)号：US20140252465A1

公开(公告)日：2014-09-11

申请号：US14352142

申请日：2012-10-17

申请人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Hidefumi Takaya ,  Hideo Matsuki ,  Naohiro Suzuki ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC分类号： H01L29/4236 ,  H01L21/047 ,  H01L21/28008 ,  H01L21/823487 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/7827

摘要： A semiconductor device has a semiconductor substrate including a body region, a drift region, a trench that extends from a surface of the semiconductor substrate into the drift region through the body region, and a source region located adjacent to the trench in a range exposed to the surface of the semiconductor substrate, the source region being isolated from the drift region by the body region. A specific layer is disposed on a bottom of the trench, and it has a characteristic of forming a depletion layer at a junction between the specific layer and the drift region. An insulating layer covers an upper surface of the specific layer and a sidewall of the trench. A conductive portion is formed on a part of the side wall of the trench. The conductive portion is joined to the specific layer, and reaches the surface of the semiconductor substrate.

摘要翻译： 半导体器件具有半导体衬底，其包括体区，漂移区，从半导体衬底的表面延伸通过体区的漂移区的沟槽，以及与暴露于 半导体衬底的表面，源区域通过身体区域与漂移区隔离。 特定层设置在沟槽的底部，并且具有在特定层和漂移区之间的结处形成耗尽层的特征。 绝缘层覆盖特定层的上表面和沟槽的侧壁。 导电部分形成在沟槽的侧壁的一部分上。 导电部分连接到特定层，并到达半导体衬底的表面。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US20120012860A1

公开(公告)日：2012-01-19

申请号：US13177747

申请日：2011-07-07

申请人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

发明人： Shinichiro MIYAHARA ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Yukihiko Watanabe

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7828

摘要： A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.

摘要翻译： SiC半导体器件包括：反向型MOSFET，具有：衬底; 衬底上的漂移层和基极区域; 基极接触层和基极区上的源极区; 多个沟槽具有沿着第一方向的纵向方向穿过源极区域和基极区域; 通过栅极绝缘膜在每个沟槽中的栅电极; 覆盖所述栅电极且具有接触孔的层间绝缘膜，所述源极区域和所述基极接触层暴露在所述接触孔中; 源极通过接触孔与源极区域和基极区域耦合; 衬底上的漏电极。 源区域和基底接触层与垂直于第一方向的第二方向一起延伸，并且与第一方向交替布置。 接触孔沿第一方向具有纵向方向。