公开(公告)号：US06207222B1

公开(公告)日：2001-03-27

申请号：US09379696

申请日：1999-08-24

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： B05D512

CPC分类号： H01L21/76843 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US07112528B2

公开(公告)日：2006-09-26

申请号：US10367214

申请日：2003-02-13

申请人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC分类号： H01L21/44 ,  H01L21/302

CPC分类号： H01L21/28562 ,  H01L21/76879

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

公开(公告)号：US06537905B1

公开(公告)日：2003-03-25

申请号：US08778205

申请日：1996-12-30

申请人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

发明人： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC分类号： H01L214763

CPC分类号： H01L21/28562 ,  H01L21/76879

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其通过填充形成在阻挡层内的金属线，优选铜，并入选择性化学气相沉积铝（CVD Al）。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US6139905A

公开(公告)日：2000-10-31

申请号：US838839

申请日：1997-04-11

申请人： Liang-Yuh Chen ,  Mehul Naik ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Mehul Naik ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： H01L21/28 ,  H01L21/203 ,  H01L21/3205 ,  H01L21/768 ,  B05D5/12

CPC分类号： H01L21/28556 ,  H01J37/32082 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877

摘要： The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons. layer is not continuous to nucleate the growth of the CVD wetting layer thereon. A PVD deposited metal is then deposited on the wetting layer at low temperature to fill the interconnect.

摘要翻译： 本发明提供一种用于形成具有高纵横比的小特征尺寸（例如四分之一微米宽度）的互连的方法和装置。 通常，本发明提供了一种用于沉积用于后续物理气相沉积以润湿互连的润湿层的方法和装置。 在本发明的一个方面，润湿层是使用CVD技术或电镀（诸如CVD铝（Al））沉积的金属层。 润湿层使用表示为+531层的超薄层作为成核层成核。 +531层优选由诸如Ti，TiN，Al，Ti / TiN，Ta，TaN，Cu的材料，TDMAT等的齐平构成。 可以使用PVD或CVD技术沉积+531层，优选PVD技术以改善特征内的膜质量和取向。 与常规智慧相反，+531层不连续以使其上的CVD润湿层的生长成核。 然后在低温下将PVD沉积的金属沉积在润湿层上以填充互连。

公开(公告)号：US6139697A

公开(公告)日：2000-10-31

申请号：US792292

申请日：1997-01-31

申请人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

发明人： Liang-Yuh Chen ,  Roderick Craig Mosely ,  Fusen Chen ,  Rong Tao ,  Ted Guo

IPC分类号： H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  C23C14/34

CPC分类号： H01L21/76877

摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.

摘要翻译： 本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。 在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。 然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。 接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。 所得到的CVD / PVD ​​Cu层基本上无空隙。 金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。 本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

公开(公告)号：US6001420A

公开(公告)日：1999-12-14

申请号：US718656

申请日：1996-09-23

申请人： Roderick Craig Mosely ,  Liang-Yuh Chen ,  Ted Guo

发明人： Roderick Craig Mosely ,  Liang-Yuh Chen ,  Ted Guo

IPC分类号： C23C16/06 ,  H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  B05D1/36 ,  C23C16/00

CPC分类号： H01L21/76864 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L2221/1089 ,  Y10S977/891

摘要： The present invention is a method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.

摘要翻译： 本发明是通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的方法。 绝缘层优先沉积在衬底的场上以延迟或抑制场上金属的成核。 然后将CVD金属沉积到衬底上并选择性地生长在接触孔中，或通过其中阻挡层用作成核层。 该方法优选在包括PVD和CVD处理室的多室系统中进行，使得一旦将基底引入真空环境中，接触孔和通孔的填充发生，而在图案上没有形成氧化物层 基质。

公开(公告)号：US5989623A

公开(公告)日：1999-11-23

申请号：US914521

申请日：1997-08-19

申请人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

发明人： Liang-Yuh Chen ,  Rong Tao ,  Ted Guo ,  Roderick Craig Mosely

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  B05D5/12

CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76807

摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

摘要翻译： 本发明通常提供用于形成高度集成的互连件的金属化工艺。 更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。 在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。 本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点， 并减少了实现这种集成的流程步骤。

公开(公告)号：US07824743B2

公开(公告)日：2010-11-02

申请号：US11864100

申请日：2007-09-28

申请人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

发明人： Wei Ti Lee ,  Yen-Chih Wang ,  Mohd Fadzli Anwar Hassan ,  Ryeun Kwan Kim ,  Hyung Chul Park ,  Ted Guo ,  Alan A. Ritchie

IPC分类号： B05D5/12 ,  H01L21/04 ,  H01L21/203 ,  H05H1/24

CPC分类号： H01J37/34 ,  C23C14/0036 ,  C23C14/0089 ,  C23C14/0641 ,  H01J37/32449 ,  H01J37/32706 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76879 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments described herein provide a method for forming two titanium nitride materials by different PVD processes, such that a metallic titanium nitride layer is initially formed by a PVD process in a metallic mode and a titanium nitride retarding layer is formed over a portion of the metallic titanium nitride layer by a PVD process in a poison mode. Subsequently, a first aluminum layer, such as an aluminum seed layer, may be selectively deposited on exposed portions of the metallic titanium nitride layer by a CVD process. Thereafter, a second aluminum layer, such as an aluminum bulk layer, may be deposited on exposed portions of the first aluminum layer and the titanium nitride retarding layer during an aluminum PVD process.

摘要翻译： 本文所述的实施例提供了通过不同PVD工艺形成两种氮化钛材料的方法，使得最初通过金属模式的PVD工艺形成金属氮化钛层，并且在金属钛的一部分上形成氮化钛延迟层 氮化物层通过PVD工艺处于毒液模式。 随后，通过CVD工艺可以在金属氮化钛层的暴露部分上选择性地沉积第一铝层，例如铝籽晶层。 此后，在铝PVD工艺期间，可以在第一铝层和氮化钛延迟层的暴露部分上沉积第二铝层，例如铝本体层。

公开(公告)号：US20060144703A1

公开(公告)日：2006-07-06

申请号：US11029641

申请日：2005-01-05

申请人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

发明人： Hong Yang ,  Tza-Jing Gung ,  Jian-Xin Lei ,  Ted Guo

IPC分类号： C23C14/00

CPC分类号： H01J37/3408 ,  H01J37/3405

摘要： A multi-track magnetron having a convolute shape and asymmetric about the target center about which it rotates. A plasma track is formed as a closed loop between opposed inner and outer magnetic poles, preferably as two or three radially arranged and spirally shaped counter-propagating tracks with respect to the target center and preferably passing over the rotation axis. The pole shape may be optimized to produce a cumulative track length distribution conforming to the function L=arn. After several iterations of computerized optimization, the pole shape may be tested for sputtering uniformity with different distributions of magnets in the fabricated pole pieces. If the uniformity remains unsatisfactory, the design iteration is repeated with a different n value, different number of tracks, or different pole widths. The optimization reduces azimuthal sidewall asymmetry and improves radial deposition uniformity.

摘要翻译： 具有卷绕形状且围绕其旋转的目标中心不对称的多轨磁控管。 等离子体轨道形成为相对的内部和外部磁极之间的闭合回路，优选地相对于目标中心并且优选地通过旋转轴线而形成为两个或三个径向布置且螺旋形的反向传播轨迹。 极点形状可以被优化以产生符合函数L = ar 的累积轨迹长度分布。 经过数次迭代的计算机化优化，可以测试极点形状，使其在制造的极片中具有不同的磁体分布的溅射均匀性。 如果均匀性不能令人满意，则使用不同的n值，不同数量的轨道或不同的极宽重复设计迭代。 优化可减少方位角侧壁不对称性，提高径向沉积均匀性。

公开(公告)号：US06528180B1

公开(公告)日：2003-03-04

申请号：US09577705

申请日：2000-05-23

申请人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

发明人： Wei Ti Lee ,  Ted Guo ,  Gongda Yao

IPC分类号： H01L2940

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76877 ,  Y10T428/12535 ,  Y10T428/12611 ,  Y10T428/12743 ,  Y10T428/12806 ,  Y10T428/26

摘要： A method for metallizing integrated circuits is disclosed. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from the group of tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.

摘要翻译： 公开了一种金属化集成电路的方法。 在一个方面，集成电路通过将衬垫材料沉积在衬底上而后接一个或多个金属层进行金属化。 衬垫材料选自钽（Ta），氮化钽（TaN），铌（Nb），氮化铌（NbN），钒（V），氮化钒（VN）及其组合。 优选使用物理气相沉积（PVD）将衬垫材料适当地沉积在衬底上。 使用化学气相沉积（CVD），物理气相沉积（PVD）或CVD和PVD的组合将一个或多个金属层沉积在阻挡层上。