公开(公告)号：US20160300836A1

公开(公告)日：2016-10-13

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

公开(公告)号：US20160225673A1

公开(公告)日：2016-08-04

申请号：US15079414

申请日：2016-03-24

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Rick L. Wise

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0684 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have semiconductor materials with higher mobilities than silicon. A fin of the n-channel finFET is on a first silicon-germanium buffer in a first trench through the dielectric layer on the substrate. A fin of the p-channel finFET is on a second silicon-germanium buffer in a second trench through the dielectric layer on the substrate. The fins extend at least 10 nanometers above the dielectric layer. The fins are formed by epitaxial growth on the silicon-germanium buffers in the trenches in the dielectric layer, followed by CMP planarization down to the dielectric layer. The dielectric layer is recessed to expose the fins. The fins may be formed concurrently or separately.

公开(公告)号：US09397100B2

公开(公告)日：2016-07-19

申请号：US14578732

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L27/092 ,  H01L21/3213

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract translation: 一种具有金属栅极NMOS晶体管的集成电路和方法，其在高质量热生长界面电介质上具有高k第一栅极电介质，并且具有在化学生长界面电介质上具有高k最后栅极电介质的金属栅极PMOS晶体管。

公开(公告)号：US09385117B2

公开(公告)日：2016-07-05

申请号：US14573006

申请日：2014-12-17

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Terry J. Bordelon, Jr. ,  Deborah J. Riley

IPC: H01L21/8248 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/66 ,  H01L29/417 ,  H01L21/265 ,  H01L29/78 ,  H01L29/737 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L27/0623 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/8249 ,  H01L23/535 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66242 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/737 ,  H01L29/7378 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/7849

Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.

Abstract translation: 形成在硅衬底上的集成电路包括具有与NMOS晶体管的栅极相邻的n沟道升高源极和漏极（NRSD）层的NMOS晶体管，在与PMOS晶体管的栅极相邻的衬底中具有SiGe应力的PMOS晶体管 ，以及在衬底中形成有p型SiGe基极的NPN异质结双极晶体管（NHBT）和形成在SiGe基底上的n型硅发射极。 SiGe应力源和SiGe基极由硅 - 锗外延形成。 NRSD层和硅发射体通过硅外延形成。

公开(公告)号：US09356131B2

公开(公告)日：2016-05-31

申请号：US14635288

申请日：2015-03-02

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Hiroaki Niimi

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

公开(公告)号：US08592902B1

公开(公告)日：2013-11-26

申请号：US13624018

申请日：2012-09-21

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L29/66

CPC classification number: H01L21/266 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823878 ,  H01L29/66477 ,  H01L29/6659 ,  H01L29/7833

Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.

Abstract translation: 通过形成具有不同掺杂剂浓度的多个n型栅极区域和具有不同掺杂剂浓度的多个p型栅极区域，半导体结构中的栅极交叉扩散被大大减少或消除，使得具有最低掺杂剂浓度的n型栅极区域接触 具有最低掺杂剂浓度的p型栅极区域。

公开(公告)号：US20250142800A1

公开(公告)日：2025-05-01

申请号：US18498559

申请日：2023-10-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra

IPC: H10B10/00

Abstract: Described examples include a semiconductor device having a first p-channel field effect transistor (p-FET). The first p-FET includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and first silicon-germanium (SiGe) regions disposed in the substrate, on both sides of the first gate structure, the first SiGe regions extended to a first depth from the surface of the substrate. The semiconductor device also has a second p-FET. The second p-FET includes a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and second SiGe regions disposed in the substrate, on both sides of the second gate structure, the second SiGe regions extended to a second depth from the surface of the substrate, the second depth different than the first depth.

公开(公告)号：US20250006804A1

公开(公告)日：2025-01-02

申请号：US18344570

申请日：2023-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Manoj Mehrotra ,  Yu-Lun Lin

IPC: H01L29/417 ,  H01L21/311 ,  H01L29/08 ,  H01L29/78

Abstract: A semiconductor device including a contact plug formed in a contact hole using a multi-stage contact etch process. The semiconductor device comprises a source/drain region over a semiconductor substrate, an oxide layer extension extending from the source/drain region toward a gate dielectric layer, and a contact plug extending through a dielectric layer over the source/drain region, the contact plug extending through a first etch stop layer and a second etch stop layer to a horizontal remaining portion of the oxide layer extension.

公开(公告)号：US20210225711A1

公开(公告)日：2021-07-22

申请号：US17202978

申请日：2021-03-16

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/11 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US20190103321A1

公开(公告)日：2019-04-04

申请号：US16206045

申请日：2018-11-30

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/8238 ,  H01L27/11 ,  H01L21/02 ,  H01L29/20 ,  H01L29/16 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.