公开(公告)号：US20120276688A1

公开(公告)日：2012-11-01

申请号：US13546684

申请日：2012-07-11

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/06

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20100019215A1

公开(公告)日：2010-01-28

申请号：US12177435

申请日：2008-07-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Thomas D. Happ ,  Matthew J. Breitwisch ,  Alejandro Gabriel Schrott ,  Min Yang

IPC分类号： H01L47/00 ,  H01L21/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括沿第一方向延伸的多个字线和覆盖多个字线并沿第二方向延伸的多个位线。 多个存储单元处于交叉点位置。 每个存储单元包括具有与相应字线的侧面对准的第一和第二侧的二极管。 每个存储单元还包括以二极管为中心的底部电极，底部电极具有表面积小于二极管顶表面的顶表面。 每个存储器单元包括在底部电极的顶表面上的存储器材料条，存储器材料条下面并与相应位线电连通。

公开(公告)号：US08273598B2

公开(公告)日：2012-09-25

申请号：US13020051

申请日：2011-02-03

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US08445313B2

公开(公告)日：2013-05-21

申请号：US13546684

申请日：2012-07-11

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20120202333A1

公开(公告)日：2012-08-09

申请号：US13020051

申请日：2011-02-03

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/02

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，其包括在下电极的一部分上形成牺牲材料的基座并且与邻近所述牺牲材料的至少一个电介质材料相连，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。

公开(公告)号：US20090261313A1

公开(公告)日：2009-10-22

申请号：US12107573

申请日：2008-04-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Min Yang ,  Alejandro Gabriel Schrott

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Min Yang ,  Alejandro Gabriel Schrott

IPC分类号： H01L45/00

CPC分类号： H01L45/143 ,  G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1666

摘要： Memory cells are described along with methods for manufacturing. A memory cell as described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a width less than that of the base portion. A dielectric surrounds the bottom electrode and has a top surface. A memory element is overlying the bottom electrode and includes a recess portion extending from the top surface of the dielectric to contact the pillar portion of the bottom electrode, wherein the recess portion of the memory element has a width substantially equal to the width of the pillar portion of the bottom electrode. A top electrode is on the memory element.

摘要翻译： 描述存储单元以及制造方法。 本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部的宽度小于基部的宽度。 电介质围绕底部电极并具有顶部表面。 存储元件覆盖在底部电极上，并且包括从电介质的顶表面延伸以与底部电极的柱部分接触的凹部，其中存储元件的凹部的宽度基本上等于柱的宽度 部分底部电极。 顶部电极位于存储元件上。

公开(公告)号：US09355887B2

公开(公告)日：2016-05-31

申请号：US13349203

申请日：2012-01-12

申请人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

发明人： Victor Chan ,  Meikei Ieong ,  Rajesh Rengarajan ,  Alexander Reznicek ,  Chun-yung Sung ,  Min Yang

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L21/76229

摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.

摘要翻译： 本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。 在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第 第一深度用于隔离相同极性的设备。 本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。 根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

公开(公告)号：US09048261B2

公开(公告)日：2015-06-02

申请号：US13198255

申请日：2011-08-04

申请人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

发明人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

IPC分类号： H01L21/44 ,  H01L21/441 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L21/31 ,  H01L21/0228 ,  H01L21/2254 ,  H01L29/165 ,  H01L29/365 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66803 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.

摘要翻译： 公开了使用原子层掺杂工艺制造的场效应晶体管。 根据原子层掺杂方法的实施方案，制备半导体表面和掺杂剂气体混合物。 此外，通过在小于500托的压力和300℃至750℃的温度下将掺杂剂气体混合物施加到半导体表面，在半导体表面上生长掺杂剂层。掺杂剂层包括在 与半导体表面上的原子反应的每立方厘米的最小4×10 20有源掺杂剂原子使得反应的原子增加了半导体表面的导电性。

公开(公告)号：US20150099744A1

公开(公告)日：2015-04-09

申请号：US14506889

申请日：2014-10-06

申请人： David Lee Tamang ,  Min Yang ,  Simon S. Jones

发明人： David Lee Tamang ,  Min Yang ,  Simon S. Jones

IPC分类号： C07D239/42 ,  A61K31/517 ,  A61K31/5377 ,  A61K31/505

CPC分类号： A61K31/505 ,  A61K31/517 ,  A61K31/519 ,  A61K31/5377 ,  A61K45/06 ,  C07D239/42 ,  A61K2300/00

摘要： The invention relates to combinations comprising an HDAC inhibitor and a Her2 inhibitor for the treatrent of breast cancer in a subject in need thereof. The invention also relates to combinations comprising an HDAC inhibitor and a PI3K inhibitor for the treatment of breast cancer in a subject in need thereof. Also provided herein are methods for treating breast cancer in a subject in need thereof comprising administering to the subject an effective amount of one of the above combinations. Further provided are methods for inhibiting migration and/or invasion of a breast cancer cell in a subject by administering to the subject a HDAC6 specific inhibitor.

摘要翻译： 本发明涉及包含HDAC抑制剂和Her2抑制剂的组合物，用于在有需要的受试者中治疗乳腺癌。 本发明还涉及包含HDAC抑制剂和PI3K抑制剂的组合，用于在有需要的受试者中治疗乳腺癌。 本文还提供了在有需要的受试者中治疗乳腺癌的方法，其包括向受试者施用有效量的上述组合之一。 还提供了通过向受试者施用HDAC6特异性抑制剂来抑制受试者中乳腺癌细胞迁移和/或侵袭的方法。

公开(公告)号：US20130032865A1

公开(公告)日：2013-02-07

申请号：US13606873

申请日：2012-09-07

申请人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

发明人： Kevin K. Chan ,  Young-Hee Kim ,  Isaac Lauer ,  Ramachandran Muralidhar ,  Dae-Gyu Park ,  Xinhui Wang ,  Min Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/31 ,  H01L21/0228 ,  H01L21/2254 ,  H01L29/165 ,  H01L29/365 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66803 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785

摘要： Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.