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公开(公告)号：US4675554A
公开(公告)日：1987-06-23
申请号：US815846
申请日：1986-01-03
IPC分类号： H03K19/013 , H03K19/086 , H03K17/16 , H03K17/60 , H03K19/02
CPC分类号： H03K19/086 , H03K19/0136
摘要： A transient driver circuit for use with a logic circuit having an emitter-follower output stage that sources current to a load connected to an output thereof in response to an applied logic signal being at a first logic level. The transient driver circuit includes a first NPN transistor the collector-emitter path of which is coupled between the output of the logic circuit and the negative power supply rail, a second NPN transistor having its collector-emitter path couple between a positive power supply rail and the collector of the first NPN transistor and its base adapted to receive the logic signal and feedback circuitry that is responsive to a rise in the collector voltage of the second NPN transistor occurring as the logic signal switches to a second logic level for supplying current drive to the base of the first NPN transistor thereby turning it on to sink a large transient current at the output of the logic circuit.
摘要翻译： 一种用于具有发射极跟随器输出级的逻辑电路的瞬态驱动器电路，其响应于所施加的逻辑信号处于第一逻辑电平而将电流供给连接到其输出的负载。 瞬态驱动器电路包括第一NPN晶体管，其集电极 - 发射极路径耦合在逻辑电路的输出端和负电源轨道之间，第二NPN晶体管的集电极 - 发射极路径耦合在正电源轨和 第一NPN晶体管的集电极及其基极适于接收响应于第二NPN晶体管的集电极电压升高而产生的逻辑信号和反馈电路，逻辑信号切换到第二逻辑电平以供应电流驱动 第一NPN晶体管的基极由此导通，以在逻辑电路的输出端吸收大的瞬态电流。
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公开(公告)号：US4570240A
公开(公告)日：1986-02-11
申请号：US566837
申请日：1983-12-29
IPC分类号： G11C11/414 , G11C11/415 , H03K17/60 , G11C7/00 , G11C8/00 , G11C11/00
CPC分类号： G11C11/415
摘要： A memory circuit is provided wherein the speed of the downward transition of the memory cell is increased. A plurality of memory cells are coupled between a select line and a current drain line. A first means is coupled to the select line for providing current to the plurality of memory cells and is responsive to a select signal having first and second states. A first PNP transistor has an emitter coupled to the current drain line for drawing any charge from the plurality of memory cells when the select signal transitions downward. A second means is coupled to the base of the first PNP transistor and is responsive to the select signal for setting the current level in said first PNP transistor. A second embodiment additionally includes a second PNP transistor having an emitter coupled to the select line and a collector coupled to said second supply voltage terminal for removing charge stored on the select line.
摘要翻译： 提供了存储器电路，其中存储单元的向下转换的速度增加。 多个存储单元耦合在选择线和电流漏极线之间。 第一装置耦合到选择线，用于向多个存储单元提供电流，并响应于具有第一和第二状态的选择信号。 当选择信号向下转变时，第一PNP晶体管具有耦合到电流漏极线的发射极，用于从多个存储器单元抽取任何电荷。 第二装置耦合到第一PNP晶体管的基极，并且响应于选择信号来设置所述第一PNP晶体管中的电流电平。 第二实施例另外包括具有耦合到选择线的发射极的第二PNP晶体管和耦合到所述第二电源电压端子的集电极，用于去除存储在选择线上的电荷。
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公开(公告)号：US4423339A
公开(公告)日：1983-12-27
申请号：US237310
申请日：1981-02-23
申请人： Walter C. Seelbach , Boyd K. Hansen
发明人： Walter C. Seelbach , Boyd K. Hansen
IPC分类号： H03K19/23 , H03K5/08 , H03K19/092 , H03K19/094
CPC分类号： H03K19/23
摘要： A majority logic gate is comprised of a plurality of depletion mode switching devices and includes Schottky diodes for both level shifting and clamping the high logic level output voltage to ground. A plurality of MESFET input devices each have their gate electrode coupled to one input of the majority logic gate. Each MESFET input device has a source coupled to ground and a drain coupled to a current load device. The voltage level at the drain at each of the input devices changes from a logical "0" to a logical "1" state depending upon the number of inputs which are at a logical "1" level. The drain voltage is then level shifted down. The high logic level output voltage is clamped to ground by means of two Schottky diodes the first of which has a cathode coupled to ground and an anode coupled to the anode of the second diode, the cathode of the second diode being coupled to the output of the circuit.
摘要翻译： 多数逻辑门由多个耗尽型开关器件组成，并包括用于电平移位并将高逻辑电平输出电压钳位到地的肖特基二极管。 多个MESFET输入装置各自具有耦合到多数逻辑门的一个输入的栅电极。 每个MESFET输入装置具有耦合到地的源极和耦合到当前负载装置的漏极。 每个输入装置的漏极处的电压电平根据逻辑“1”电平的输入数从逻辑“0”变为逻辑“1”状态。 然后漏极电压向下移位。 高逻辑电平输出电压通过两个肖特基二极管钳位到地，第一个肖特基二极管具有耦合到地的阴极和耦合到第二二极管的阳极的阳极，第二二极管的阴极耦合到 电路。
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公开(公告)号：US4223238A
公开(公告)日：1980-09-16
申请号：US934642
申请日：1978-08-17
CPC分类号： G05F3/205
摘要： An integrated circuit is disclosed which includes a charge pump adapted for biasing the substrate of a monolithic integrated circuit containing bipolar transistors. An oscillator operating under the control of a control input provides pulsed output signals for driving a diode-capacitor voltage multiplier network which generates a substrate bias voltage. A feedback network including a zener diode senses the substrate voltage, and switching action of the zener diode operates to selectively enable and disable the oscillator for regulating the substrate bias voltage.
摘要翻译： 公开了一种集成电路，其包括适于偏置包含双极晶体管的单片集成电路的衬底的电荷泵。 在控制输入的控制下工作的振荡器提供脉冲输出信号，用于驱动产生衬底偏置电压的二极管 - 电容器电压倍增器网络。 包括齐纳二极管的反馈网络感测衬底电压，并且齐纳二极管的开关动作用于选择性地使能和禁止用于调节衬底偏置电压的振荡器。
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公开(公告)号：US6023189A
公开(公告)日：2000-02-08
申请号：US650023
申请日：1996-05-17
申请人： Walter C. Seelbach
发明人： Walter C. Seelbach
CPC分类号： G05F3/30
摘要： A low voltage submicron CMOS circuit (10) for providing an output bandgap voltage (V.sub.BG) that is substantially independent of temperature and power supply variations has been provided. The CMOS circuit utilizes parasitic transistors (28-30) to create a delta voltage that has a positive temperature coefficient across a differential pair of NMOS transistors (14, 16). This delta voltage is then converted into differential currents which are amplified and mirrored and summed together to provide an output current (I.sub.O) that has a positive temperature coefficient. This output current is then passed through a series network including a resistor element (52) and a parasitic PNP junction transistor (31) to provide a bandgap voltage of 1.2 volts wherein the voltage across the resistor element has a positive temperature coefficient and the voltage across the parasitic PNP junction transistor has an inherent negative temperature coefficient.
摘要翻译： 已经提供了用于提供基本上与温度和电源变化无关的输出带隙电压（VBG）的低电压亚微米CMOS电路（10）。 CMOS电路利用寄生晶体管（28-30）产生跨越NMOS晶体管（14,16）的差分对的正温度系数的增量电压。 然后将该增量电压转换成差分电流，这些电流被放大并镜像并相加在一起以提供具有正温度系数的输出电流（IO）。 然后，该输出电流通过包括电阻元件（52）和寄生PNP结晶体管（31）的串联网络，以提供1.2伏的带隙电压，其中电阻元件两端的电压具有正温度系数和 寄生PNP结晶体管具有固有的负温度系数。
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公开(公告)号：US5120998A
公开(公告)日：1992-06-09
申请号：US664896
申请日：1991-03-04
IPC分类号： H03K19/086 , H03F3/72 , H03K19/0175 , H03K19/018 , H04L25/08
CPC分类号： H04L25/08 , H03K19/01825
摘要： A source terminated transmission line driver circuit having an output coupled to a transmission line through a resistor is provided. The driver circuit has a gate circuit for providing first and second signals and a pulse generator circuit responsive to the second signal of the gate circuit for providing a pulse current at an output when the second signal is switching from a first logic state to a second logic state and for otherwise providing a quiescent current at the output. The driver circuit also has a first circuit responsive to the first output signal of the gate circuit for sourcing current to the output of the source terminated transmission line driver circuit, the first circuit being responsive to the second output signal of the gate circuit for sinking an adjustable current at the output of the source terminated transmission line driver circuit. The first circuit has a first transistor having a collector, a base and an emitter, the emitter being coupled to the output of the source terminated transmission line driver circuit, the base being coupled to receive the first signal of the gate circuit, and the collector being coupled to the first supply voltage terminal, a second transistor having a collector, a base and an emitter, the emitter of the second transistor being coupled to the output of the source terminated transmission line driver circuit, the base of the second transistor being coupled to the output of the pulse generator circuit, the collector being coupled to a second supply voltage terminal, a third transistor having a collector, a base and an emitter, the collector of the third transistor being coupled to the first supply voltage terminal, the base of the third transistor being coupled to the base of the first transistor, and a fourth transistor having a collector, a base and an emitter, the collector and base of the fourth transistor being coupled to the emitter of the third transitor, the emitter of the fourth transistor being coupled to the base of the second transistor.
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公开(公告)号：US5047707A
公开(公告)日：1991-09-10
申请号：US615684
申请日：1990-11-19
摘要： A circuit is provided that generates a predetermined regulated voltage between first and second terminals that is positioned between first and second power supply voltage rails wherein the predetermined regulated voltage is substantially independent of temperature and power supply variation. The circuit includes a bandgap circuit for providing a predetermined reference potential that is substantially independent of temperature and power supply variation. A resistive circuit provides first and second voltages which are referenced with respect to the first supply voltage rail. A level translator circuit translates the second voltage provided by the resistive circuit to a third voltage which is referenced with respect to the second supply voltage rail. First and second operational amplifier circuits are provided for respectively transferring the first and third voltages respectively to first and second terminals wherein a voltage developed between the first and second terminals is substantially equal to the predetermined reference voltage of the bandgap circuit.
摘要翻译： 提供一种电路，其产生位于第一和第二电源电压轨之间的第一和第二端子之间的预定调节电压，其中预定调节电压基本上与温度和电源变化无关。 电路包括用于提供基本上独立于温度和电源变化的预定参考电位的带隙电路。 电阻电路提供相对于第一电源电压轨参考的第一和第二电压。 电平转换器电路将由电阻电路提供的第二电压转换为相对于第二电源电压轨参考的第三电压。 提供了第一和第二运算放大器电路，用于分别将第一和第三电压分别传送到第一和第二端子，其中在第一和第二端子之间产生的电压基本上等于带隙电路的预定参考电压。
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公开(公告)号：US4730278A
公开(公告)日：1988-03-08
申请号：US914957
申请日：1986-10-03
CPC分类号： G11C8/08
摘要： A circuit is described that provides a quick charge and discharge of a row of memory cells. A first transistor has its collector-emitter path coupled between a first voltage and a row of memory cells, and a base coupled to an input terminal. A second transistor has its collector-emitter path coupled to the first voltage by a resistor and to a voltage level setting device, and a base coupled to the input terminal. A third transistor has its collector-emitter path coupled between the row of memory cells and a second voltage, and a base coupled to a voltage level shifting device. As the row of memory cells are selected, the third transistor becomes less conductive, thereby sinking less current from the row of memory cells and allowing the inherent capacitance of the row of memory cells to charge more quickly. As the row of memory cells are deselected, the third transistor becomes more conductive, thereby sinking more current from the row of memory cells and discharging the inherent capacitance more quickly.
摘要翻译： 描述了提供一行存储器单元的快速充电和放电的电路。 第一晶体管具有耦合在第一电压和一行存储器单元之间的集电极 - 发射极路径，以及耦合到输入端子的基极。 第二晶体管的集电极 - 发射极路径通过电阻器和电压电平设置装置耦合到第一电压，以及耦合到输入端子的基极。 第三晶体管具有耦合在该行存储单元和第二电压之间的集电极 - 发射极路径，以及耦合到电压电平移位装置的基极。 当选择存储单元行时，第三晶体管变得较少导电，从而从存储单元行中吸收更少的电流，并允许存储单元行的固有电容更快地充电。 当存储器单元行被取消选择时，第三晶体管变得更加导电，从而从存储单元行中吸收更多的电流并且更快地对固有电容进行放电。
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公开(公告)号：US4644194A
公开(公告)日：1987-02-17
申请号：US748362
申请日：1985-06-24
IPC分类号： H03K19/003 , H03K19/018 , H03K17/10 , H03K17/14 , H03K19/092
CPC分类号： H03K19/00376 , H03K19/01812
摘要： A voltage level translator circuit is provided that translates an input voltage referenced to an ECL supply voltage V.sub.CC to a voltage referenced to a TTL supply voltage V.sub.EE independent of power supply voltage variations. A first and a second embodiment have reference circuits coupled to receive a data input signal for providing a single signal referenced to a first supply voltage terminal to a current mirror. An output circuit is coupled to the current mirror for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled to receive a data input signal for referencing a voltage on a first supply voltage terminal to a voltage on a second supply voltage terminal. A voltage setting circuit is coupled to the reference circuit for setting a voltage within the reference circuit. An output circuit is coupled to the voltage setting circuit for providing an output voltage referenced to a voltage on the second voltage terminal and independent of variations in supply voltages.
摘要翻译： 提供电压电平转换器电路，其将参考ECL电源电压VCC的输入电压转换为与电源电压变化无关的TTL电源电压VEE。 第一和第二实施例具有耦合以接收数据输入信号的参考电路，用于将参考第一电源电压端子的单个信号提供给电流镜。 输出电路耦合到电流镜，用于提供参考第二电源电压端子的输出信号。 第三实施例具有耦合以接收数据输入信号的参考电路，用于将第一电源电压端子上的电压参考为第二电源电压端子上的电压。 电压设定电路与参考电路耦合，用于设定参考电路内的电压。 输出电路耦合到电压设置电路，用于提供参考第二电压端子上的电压的输出电压，并且与电源电压的变化无关。
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20.发明授权Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection 失效具有埋置氧化物隔离的集成电路和用于电源互连的低电阻衬底
公开(公告)号：US4631570A
公开(公告)日：1986-12-23
申请号：US628019
申请日：1984-07-03
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8222 , H01L23/528 , H01L27/06 , H01L27/082 , H01L27/12 , H01L27/02
CPC分类号： H01L21/76243 , H01L23/5286 , H01L27/0825 , H01L2924/0002 , Y10S148/083 , Y10S148/085 , Y10S257/906
摘要： An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.
摘要翻译： 公开了一种集成电路电源互连技术，其具有用于分配集成电路最正电源电压的高掺杂的低电阻率衬底。 衬底作为最正的电压点，并且适应通常直接连接到最正电源电压的器件。 电介质掩埋层覆盖在衬底的一部分上，并将衬底电源电压与不直接连接到最正电源电压的器件隔离。
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