公开(公告)号：US20220238380A1

公开(公告)日：2022-07-28

申请号：US17486189

申请日：2021-09-27

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20210265253A1

公开(公告)日：2021-08-26

申请号：US17096595

申请日：2020-11-12

Applicant: Tokyo Electron Limited

Inventor： Arya BHATTACHERJEE ,  H. Jim FULFORD

IPC: H01L23/498 ,  H01L21/48

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials. The interface wiring plane is electrically connected to the passive electrical device and electrically connects at least one of the first TSVs to at least one of the second TSVs.

公开(公告)号：US20210175128A1

公开(公告)日：2021-06-10

申请号：US16927462

申请日：2020-07-13

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/8238 ,  H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/033 ,  H01L21/02 ,  H01L29/66

Abstract: Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can enable higher density circuits to be produced at reduced cost. The methods can include growth of channel regions and S/D regions for NMOS devices using a first same nano-sheet in a nano-sheet stack. Similarly, the methods can include growth of channel regions and S/D regions for PMOS devices using a second same nano-sheet in the nano-sheet stack. The resulting 3D CMOS stack can include integrated channel and S/D regions.

公开(公告)号：US20250081552A1

公开(公告)日：2025-03-06

申请号：US18458688

申请日：2023-08-30

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/778

Abstract: A semiconductor device is provided. The semiconductor device includes a pair of channel structures each configured to have a current direction along a first direction substantially parallel to a working surface of a substrate. The semiconductor device also includes source/drain (S/D) structures on opposing sides of the pair of channel structures along the first direction. The semiconductor device further includes a gate structure between the pair of channel structures. The pair of channel structures includes two-dimensional (2D) semiconductor material oriented substantially perpendicular to the working surface of the substrate.

公开(公告)号：US20230301059A1

公开(公告)日：2023-09-21

申请号：US17959771

申请日：2022-10-04

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally; an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally; a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor, the lower metal capacitor including a first lower metal plate, a lower dielectric layer that surrounds the first lower metal plate, and a second lower metal plate that surrounds the lower dielectric layer; and an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor, the upper metal capacitor including a first upper metal plate, an upper dielectric layer that surrounds the first upper metal plate, and a second upper metal plate that surrounds the upper dielectric layer.

公开(公告)号：US20230262956A1

公开(公告)日：2023-08-17

申请号：US17946690

申请日：2022-09-16

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/08 ,  H01L29/786 ,  H01L21/8234

CPC classification number: H01L27/10805 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/1085 ,  H01L27/10873 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

公开(公告)号：US20230261113A1

公开(公告)日：2023-08-17

申请号：US18093205

申请日：2023-01-04

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L27/088 ,  H01L25/065 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/78618 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66742 ,  H01L29/78642 ,  H01L29/78696 ,  H01L27/088 ,  H01L25/0657 ,  H01L21/762 ,  H01L21/76816 ,  H01L21/76819 ,  H01L21/7684 ,  H01L21/76877

Abstract: A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.

公开(公告)号：US20230251584A1

公开(公告)日：2023-08-10

申请号：US17889460

申请日：2022-08-17

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/20 ,  H01L21/67 ,  H01L21/324 ,  H01L21/66

CPC classification number: G03F7/70783 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/3247 ,  H01L22/20 ,  H01L21/67288 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

公开(公告)号：US20230207660A1

公开(公告)日：2023-06-29

申请号：US17957076

申请日：2022-09-30

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/762 ,  H01L29/40

CPC classification number: H01L29/66439 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/76251 ,  H01L29/401

Abstract: A method of forming a vertical channel transistor includes forming a first source-drain (SD) contact on a first surface of a semiconductor device layer; and forming a second SD contact layer on a second surface of the semiconductor device layer, the second surface being opposite to the first surface. The semiconductor device layer is pattern etched to form a vertical channel structure having a first end connected to the first SD contact and a second end opposite to the first end and connected to the second SD contact. A gate-all-around (GAA) structure is formed to completely surrounding at least a portion of the vertical channel structure at a position between the first SD contact and the second SD contact.

公开(公告)号：US20230024788A1

公开(公告)日：2023-01-26

申请号：US17742107

申请日：2022-05-11

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

Abstract: Techniques herein include methods of forming channel structures for field effect transistors having a channel current path parallel to a surface of a substrate. 3D in-situ horizontal or lateral growth of the channel and source/drain regions allows for a custom doping in the 3D horizontal nanosheet direction for NMOS and PMOS devices. An ultra-short channel length is achieved with techniques herein because the channel is epitaxially grown in the 3D horizontal nanosheet direction at the monolayer level. Since the channel is grown in a dielectric cavity, a precise channel cross sectional area can be tuned.