公开(公告)号：US20230337435A1

公开(公告)日：2023-10-19

申请号：US18336678

申请日：2023-06-16

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H10B51/20 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H10B51/20 ,  H10B51/10 ,  H10B53/10 ,  H10B53/20 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7869 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/41733 ,  H01L21/823412 ,  H01L21/823418

Abstract: A semiconductor structure includes one or more first nanostructures extending along a first lateral direction; one or more second nanostructures extending along the first lateral direction and vertically disposed above the one or more first nanostructures; and a gate structure extending along a second lateral direction perpendicular to the first lateral direction, and disposed around each of the one or more first nanostructures and each of the one or more second nanostructures. The gate structure comprises: (i) a first metal material, (ii) a ferroelectric material, and (iii) a second metal material.

公开(公告)号：US20230301060A1

公开(公告)日：2023-09-21

申请号：US17971219

申请日：2022-10-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include a lower transistor including a lower channel that is elongated horizontally, and an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally. The semiconductor structure can also include a lower metal capacitor electrically connected to and horizontally elongated from the lower transistor. The lower metal capacitor can include a first lower metal plate that is in-plane with the lower channel of the lower transistor. The semiconductor structure can also include an upper metal capacitor vertically stacked over the lower metal capacitor and electrically connected to and horizontally elongated from the upper transistor. The upper metal capacitor can include a first upper metal plate that is in-plane with the upper channel of the upper transistor.
method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having

公开(公告)号：US20250056810A1

公开(公告)日：2025-02-13

申请号：US18448086

申请日：2023-08-10

Applicant: Tokyo Electron Limited

Inventor： Henry Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H10B53/30

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The semiconductor device includes a first semiconductor structure extending along a vertical direction; a high-k dielectric layer disposed around at least the first semiconductor structure; a first metal structure disposed around the first semiconductor structure, with the high-k dielectric layer interposed therebetween; a ferroelectric structure disposed around the first semiconductor structure, with the high-k dielectric layer and the first metal structure interposed therebetween; and a second metal structure having a portion disposed around the first semiconductor structure, with the high-k dielectric layer, the first metal structure, and the ferroelectric structure interposed therebetween.

公开(公告)号：US20230301062A1

公开(公告)日：2023-09-21

申请号：US18075242

申请日：2022-12-05

Applicant: Tokyo Electron Limited

Inventor： Mark I. GARDNER ,  H. Jim FULFORD ,  Partha MUKHOPADHYAY

IPC: H10B12/00 ,  H01L25/065 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/1085 ,  H01L25/0657 ,  H01L29/42392 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor device includes a memory cell unit positioned over a substrate. The memory cell unit includes a transistor and a capacitor. The capacitor includes an inner conductor, a capacitor dielectric all around the inner conductor, an outer conductor all around the capacitor dielectric, and dielectric support structures below the inner conductor. The capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction. The transistor includes a channel structure, a gate structure all around the channel structure, and source/drain (S/D) regions on opposing ends of the channel structure.

公开(公告)号：US20230057139A1

公开(公告)日：2023-02-23

申请号：US17740691

申请日：2022-05-10

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L23/522 ,  H01L21/3105 ,  H01L21/762

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.

公开(公告)号：US20220367289A1

公开(公告)日：2022-11-17

申请号：US17480380

申请日：2021-09-21

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L21/8234 ,  H01L21/822 ,  H01L21/768

Abstract: Aspects of the present disclosure provide a method for forming a semiconductor structure having separated vertical channel structures. The method can include forming a layer stack on a substrate, the layer stack including alternating metal layers and dielectric layers. The method can further include forming vertically stacked lower and upper vertical channel structures vertically extending through the layer stack, the lower and upper vertical channel structures being separated by a sacrificial layer. The method can further include forming source, drain and gate connections to the lower and upper vertical channel structures, the source, drain and gate connections extending horizontally from the lower and upper vertical channel structures and then vertically to a location above the upper vertical channel structure. The method can further include forming a vertical opening in the layer stack and removing the sacrificial layer through the vertical opening to separate the lower and upper vertical channel structures.

公开(公告)号：US20220359312A1

公开(公告)日：2022-11-10

申请号：US17453212

申请日：2021-11-02

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L21/8238 ,  H01L21/822 ,  H01L27/092 ,  H01L29/78

Abstract: A method of microfabrication includes epitaxially growing a first vertical channel structure of silicon-containing material on a first sacrificial layer of silicon containing material, the first sacrificial layer having etch selectivity with respect to the vertical channel structure. A core opening is directionally etched through the vertical channel structure to expose the first sacrificial layer, and the first sacrificial layer is isotropically etched through the core opening to form a first isolation opening for isolating the first vertical channel structure.

公开(公告)号：US20240282771A1

公开(公告)日：2024-08-22

申请号：US18172595

申请日：2023-02-22

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A method of fabricating a semiconductor device includes forming a patterned stack of layers including at least one lower active layer for forming a lower transistor and at least one upper active layer for forming an upper transistor stacked on the lower transistor. A dummy gate is formed surrounding a gate portion of each of the lower active layers and each of the upper active layers in the patterned stack, and the source-drain portions of the lower active layers and the upper active layers are doped. Source-drain connections to doped source-drain portions of the lower active layers and the upper active layers are formed. The dummy gate of the lower active layers and the upper active layers is replaced with a gate-all-around (GAA) structure to form the lower transistor and the upper transistor.

公开(公告)号：US20230352581A1

公开(公告)日：2023-11-02

申请号：US17730824

申请日：2022-04-27

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L29/78 ,  H01L29/22 ,  H01L29/24 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66 ,  H01L29/40

CPC classification number: H01L29/7827 ,  H01L29/22 ,  H01L29/24 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/401

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a first bottom contact positioned in a dielectric layer over a substrate, and a first channel structure extending from and in contact with the first bottom contact in a vertical direction perpendicular to the substrate. The first channel structure includes a bottom portion over the first bottom contact, a middle portion over the bottom portion, and a top portion over the middle portion. The semiconductor device includes a first gate structure positioned around the middle portion of the first channel structure, and a first top contact positioned over and in contact with the top portion of the first channel structure.

公开(公告)号：US20230320069A1

公开(公告)日：2023-10-05

申请号：US17989348

申请日：2022-11-17

Applicant: Tokyo Electron Limited

Inventor： H. Jim FULFORD ,  Mark I. GARDNER ,  Partha MUKHOPADHYAY

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873

Abstract: Aspects of the present disclosure provide a semiconductor structure, which can include a lower transistor including a lower channel that is elongated horizontally and includes a lower doped first-type semiconductor layer of a lower doped semiconductor layer, an upper transistor vertically stacked over the lower transistor and including an upper channel that is elongated horizontally and includes an upper doped first-type semiconductor layer of an upper doped semiconductor layer, a lower capacitor electrically connected to and horizontally elongated from the lower transistor and including a first lower plate that includes a lower doped second-type semiconductor layer of the lower doped semiconductor layer, and an upper capacitor vertically stacked over the lower capacitor and electrically connected to and horizontally elongated from the upper transistor and including a first upper plate that includes an upper doped second-type semiconductor layer of the upper doped semiconductor layer.