公开(公告)号：US07586272B2

公开(公告)日：2009-09-08

申请号：US11448438

申请日：2006-06-07

申请人： Makio Iida ,  Norimasa Furukawa

发明人： Makio Iida ,  Norimasa Furukawa

IPC分类号： H05B37/02

CPC分类号： H05B41/2858 ,  H01J61/547 ,  H01J61/78 ,  H05B41/2806 ,  H05B41/282 ,  Y02B20/22 ,  Y10S315/01

摘要： A cold cathode fluorescent lamp apparatus has a cold cathode fluorescent lamp which can be lit readily and in which leak current is minimized. A pair of internal electrodes are disposed on an inner surface of the cold cathode fluorescent lamp, and a pair of external electrodes are provided on an outer surface of the cold cathode fluorescent lamp. The internal electrodes are driven by a dc driving circuit, and the current flow between the internal electrodes is controlled by a constant current circuit. The external electrodes are driven by an ac driving circuit.

摘要翻译： 冷阴极荧光灯装置具有可以容易地点亮并且泄漏电流最小化的冷阴极荧光灯。 一对内部电极设置在冷阴极荧光灯的内表面上，一对外部电极设置在冷阴极荧光灯的外表面上。 内部电极由直流驱动电路驱动，内部电极之间的电流由恒定电流电路控制。 外部电极由交流驱动电路驱动。

公开(公告)号：US06242787B1

公开(公告)日：2001-06-05

申请号：US08748896

申请日：1996-11-15

申请人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/063 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.

摘要翻译： 一种包括减小表面场强度型LDMOS晶体管的半导体器件，其可以防止当向其漏极施加反向电压时在沟道形成部分处的元件的击穿。 在N型衬底中形成P阱和N阱以产生双阱结构，其中源极被设置为与N型衬底的电位相等。 N阱的漂移区域具有掺杂浓度以满足所谓的RESURF条件，其可以提供高的击穿电压低导通电阻。 当向漏极施加反向电压时，包括N阱，P阱和N型衬底的寄生双极晶体管形成朝向衬底的通电路径，使得元件在沟道形成时击穿 在施加反向电压时部分是可避免的。

公开(公告)号：US5753943A

公开(公告)日：1998-05-19

申请号：US612285

申请日：1996-03-07

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/749

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

公开(公告)号：US5644157A

公开(公告)日：1997-07-01

申请号：US653924

申请日：1996-05-22

申请人： Makio Iida ,  Shoji Miura ,  Takayuki Sugisaka ,  Toshio Sakakibara ,  Osamu Ishihara

发明人： Makio Iida ,  Shoji Miura ,  Takayuki Sugisaka ,  Toshio Sakakibara ,  Osamu Ishihara

IPC分类号： H01L21/762 ,  H01L29/73 ,  H01L29/732 ,  H01L27/06 ,  H01L29/80

CPC分类号： H01L29/7317 ,  H01L21/76264 ,  H01L29/7322 ,  H01L21/76275 ,  H01L21/76286

摘要： A semiconductor device which can compatibly achieve the improvement of the withstand voltage and the integration degree. A PN junction between a buried collector region 3 and a collector withstand voltage region 4 is subjected to reverse bias, and a depletion layer in the PN junction reaches a side dielectric isolation region 9a which dielectrically isolates the side of the collector withstand voltage region 4. A circumferential semiconductor region 14 which is in adjacency to the collector withstand voltage with the side dielectric isolation region 9a therebetween has an electric potential that is approximate to that at a base region 5 rather than that at the buried collector region 3. As a result, the depletion layer is subjected to the effect of low electric potential from both the base region 5 and the circumferential semiconductor region 14. This mitigates electrostatic focusing in the vicinity of the corner parts between the sides of the base region 5 and the bottom thereof, restraining the avalanche breakdown there and improving the withstand voltage there.

摘要翻译： 能兼容地实现耐压提高和集成度的半导体装置。 掩埋集电极区域3和集电极耐压区域4之间的PN结经受反向偏压，并且PN结中的耗尽层到达介电隔离区域9a，该介电隔离区域9a介电地隔离集电极耐压区域4的侧面。 与其间的侧绝缘隔离区域9a相邻的集电极耐电压的周向半导体区域14具有接近于基极区域5处的电位，而不是埋藏集电极区域3的电位。结果， 耗尽层受到基极区域5和周围半导体区域14两者的低电位的影响。这减轻了基部区域5的侧面与其底部之间的角部附近的静电聚焦，约束 雪崩击穿，并提高耐压。

公开(公告)号：US5503878A

公开(公告)日：1996-04-02

申请号：US292050

申请日：1994-08-18

申请人： Mikimasa Suzuki ,  Makio Iida ,  Makoto Muto

发明人： Mikimasa Suzuki ,  Makio Iida ,  Makoto Muto

IPC分类号： H01C17/06 ,  H01C17/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H05H1/00

CPC分类号： H01L28/24

摘要： A method of preparing a patterned thin film resistor that is appropriately used in combination with semiconductor devices. The method comprises a thin film forming step comprising forming a thin film of a compound comprising at least one metal on an oxide film such as a silicon oxide film; a masking step comprising covering a desired area of the thin film by an organic material; a patterning step comprising converting to plasma a gas mixture comprising a fluorine compound gas and oxygen, and removing an area of the thin film, that is not covered by the organic material by exposing it to a gas containing activated fluorine by the plasma conversion; and a removing step comprising removing the organic material remaining on the desired area of the thin film.

摘要翻译： 一种制备适合与半导体器件组合使用的图案化薄膜电阻器的方法。 该方法包括薄膜形成步骤，包括在诸如氧化硅膜的氧化膜上形成包含至少一种金属的化合物的薄膜; 掩模步骤，包括用有机材料覆盖所述薄膜的期望区域; 一种图形化步骤，包括将包含氟化合物气体和氧气的气体混合物转化成等离子体，并且通过用等离子体转换将其暴露于含有活性氟的气体中来除去未被有机材料覆盖的薄膜区域; 以及去除步骤，包括去除残留在所述薄膜的所需区域上的有机材料。

公开(公告)号：US5449946A

公开(公告)日：1995-09-12

申请号：US208119

申请日：1994-03-09

申请人： Toshio Sakakibara ,  Makio Iida ,  Takayuki Sugisaka ,  Shoji Miura

发明人： Toshio Sakakibara ,  Makio Iida ,  Takayuki Sugisaka ,  Shoji Miura

IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L21/763 ,  H01L21/822 ,  H01L27/04 ,  H01L29/06 ,  H01L27/02

CPC分类号： H01L21/76264 ,  H01L21/743 ,  H01L21/763 ,  H01L21/76275 ,  H01L21/76286

摘要： A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.

摘要翻译： 提供了一种半导体器件，其中在导电材料上非常简单地形成接触，以防止电容耦合。 两个硅衬底通过氧化硅膜结合。 并且在硅基板之一中形成延伸到氧化硅膜的沟槽，以便在多个电路元件之间彼此隔离，并且通过沟槽隔室形成用于电路元件形成的岛。 在用于电路元件形成的岛的外周部分上形成氧化硅膜。 此外，用于电容耦合防止的岛由用于电路元件形成的岛之间的硅衬底形成，并且被施加到其上以保持恒定的电位。

公开(公告)号：US5225286A

公开(公告)日：1993-07-06

申请号：US897818

申请日：1992-06-12

申请人： Hisayoshi Fujikawa ,  Yasunori Taga ,  Makio Iida

发明人： Hisayoshi Fujikawa ,  Yasunori Taga ,  Makio Iida

IPC分类号： C01G35/00 ,  H01B3/00 ,  H01B3/12 ,  H01G4/12 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L29/51

CPC分类号： H01L29/513 ,  H01L28/40 ,  H01L29/517 ,  Y10S428/901 ,  Y10S428/917 ,  Y10T428/265

摘要： A tantalum oxide dielectric film includes tantalum oxide (Ta.sub.2 O.sub.5) as a major component, and at least one oxide selected from the group consisting of yttrium oxide (Y.sub.2 O.sub.3), tungsten oxide (WO.sub.3) and niobium oxide (Nb.sub.2 O.sub.5). This dielectric film exhibits a remarkably improved dielectric constant and insulation property because it is a composite oxide film in which Ta.sub.2 O.sub.5 is compounded with Y.sub.2 O.sub.3, WO.sub.3 or Nb.sub.2 O.sub.5. For example, when the dielectric film is used as a capacitor film, the capacitor film exhibits a figure of merit, i.e., a product of a dielectric constant and an insulation property, approximately twice the silicon oxide (SiO.sub.2) film which is used widely for the purpose at present.

摘要翻译： 钽氧化物电介质膜包括作为主要成分的氧化钽（Ta 2 O 5）和选自氧化钇（Y 2 O 3），氧化钨（WO 3）和氧化铌（Nb 2 O 5）的至少一种氧化物。 该介电膜由于是与Y 2 O 3，WO 3或Nb 2 O 5复合而成的复合氧化物膜，所以介电常数和绝缘性能显着提高。 例如，当将电介质膜用作电容器膜时，电容器膜呈现出一个品质因数，即介电常数和绝缘性的乘积，大约是二氧化硅（SiO 2）膜的两倍，其广泛用于 目前的目的

公开(公告)号：US06831331B2

公开(公告)日：2004-12-14

申请号：US09945621

申请日：2001-09-05

申请人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/1087 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

摘要翻译： 提供具有功率晶体管结构的半导体器件。 功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极 表示感性负载。

公开(公告)号：US06287933B1

公开(公告)日：2001-09-11

申请号：US08015268

申请日：1992-01-03

申请人： Makio Iida ,  Shoji Miura ,  Kanemitsu Terada ,  Hiroyuki Ban ,  Kiyoshi Yamamoto ,  Katsuyoshi Oda ,  Yoshihiko Isobe

发明人： Makio Iida ,  Shoji Miura ,  Kanemitsu Terada ,  Hiroyuki Ban ,  Kiyoshi Yamamoto ,  Katsuyoshi Oda ,  Yoshihiko Isobe

IPC分类号： H01L2120

CPC分类号： H01L28/24

摘要： A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.

摘要翻译： 一种具有薄膜电阻器的半导体器件，该薄膜电阻器至少包含铬，硅和氮，并且形成在具有特定比例的化学成分的基板上，该半导体器件具有使其由于温度导致的电阻值的变化的特性 可以有效地抑制变化。

公开(公告)号：US6104078A

公开(公告)日：2000-08-15

申请号：US941756

申请日：1997-09-30

申请人： Makio Iida ,  Mitsuhiro Saitou ,  Akitaka Murata ,  Hiroyuki Ban ,  Tadashi Suzuki ,  Toshio Sakakibara ,  Takayuki Sugisaka ,  Shoji Miura

发明人： Makio Iida ,  Mitsuhiro Saitou ,  Akitaka Murata ,  Hiroyuki Ban ,  Tadashi Suzuki ,  Toshio Sakakibara ,  Takayuki Sugisaka ,  Shoji Miura

IPC分类号： H01L21/762 ,  H01L29/36

CPC分类号： H01L21/76264

摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

摘要翻译： 一种半导体器件，包括具有主表面的半导体衬底。 绝缘膜形成在半导体衬底的主表面上。 半导体层被放置在绝缘膜上。 从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。 元件区域通过侧绝缘区域和绝缘膜彼此隔离。 半导体基板的电阻率为1.5欧姆·厘米或更低。 将半导体衬底处的电压设定为给定电压。