公开(公告)号：US6146947A

公开(公告)日：2000-11-14

申请号：US54493

申请日：1998-04-03

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

摘要翻译： 在绝缘栅型场效应晶体管及其制造方法中，通过热扩散在氧化气氛下在半导体衬底中形成扩散区，并且通过气相在半导体衬底上形成第一导电类型半导体层 形成扩散区后的外延。 此后，半导体层的表面变平，在平坦的半导体层上形成栅极绝缘膜和栅电极。 此外，在半导体层中形成阱区以及源极区，形成绝缘栅型场效应晶体管。 由于形成绝缘栅型场效应晶体管的半导体层的表面平坦化，即使在晶片中形成嵌入区域，也可以防止栅源绝缘耐压特性劣化。

公开(公告)号：US5753943A

公开(公告)日：1998-05-19

申请号：US612285

申请日：1996-03-07

申请人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

发明人： Naoto Okabe ,  Makio Iida ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L21/322 ,  H01L21/331 ,  H01L21/336 ,  H01L29/08 ,  H01L29/739 ,  H01L29/749

CPC分类号： H01L29/66333 ,  H01L21/3221 ,  H01L29/0834 ,  H01L29/7395 ,  Y10S257/913

摘要： In an insulated gate type field effect transistor and a manufacturing method of the same, a diffusion region is formed in a semiconductor substrate under an oxidizing atmosphere by thermal diffusion, and a first conductivity type semiconductor layer is formed on the semiconductor substrate by vapor-phase epitaxy after the formation of the diffusion region. Thereafter, the surface of the semiconductor layer is flattened, and a gate insulating film and a gate electrode are formed on the flattened semiconductor layer. Further, a well region as well as a source region are formed in the semiconductor layer to form an insulated gate type field effect transistor. As the surface of the semiconductor layer in which the insulated gate type field effect transistor is formed is flattened, even if the embedded region is formed in the wafer, the gate-source insulation withstand voltage characteristic can be prevented from being deteriorated.

公开(公告)号：US5519245A

公开(公告)日：1996-05-21

申请号：US56946

申请日：1993-05-05

申请人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

发明人： Norihito Tokura ,  Naoto Okabe ,  Naohito Kato

IPC分类号： H01L29/08 ,  H01L29/739 ,  H01L29/80 ,  H01L23/58 ,  H01L29/76 ,  H01L29/861

CPC分类号： H01L29/0834 ,  H01L29/7395 ,  H01L2924/0002

摘要： An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

摘要翻译： 绝缘栅双极晶体管内置有反向导通功能。 第一导电类型的半导体层形成在漏极侧，在第一导电类型的半导体层上形成用于在载流子注入时引起导电性调制的第二导电类型的半导体层，第二导电类型的半导体层 在与漏电极电连接的第二导电类型的半导体层中形成用于取出与漏电流方向相反的反向导通电流的导通型，并且在第二导电类型的半导体层中形成第二导电类型的半导体层 pn结的附近，赋予和接收载流子以引起电导率调制的pn结附近，杂质浓度高，导致反向导通电流进入不妨碍载流子通过的图案的路径。 因此，内置的反向导通功能具有低的工作电阻，可以通过大的反向电流，导通电阻不增加，并且可以缩短关断时间。

公开(公告)号：US5973338A

公开(公告)日：1999-10-26

申请号：US947402

申请日：1997-10-08

申请人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

发明人： Naoto Okabe ,  Norihito Tokura ,  Naohito Kato

IPC分类号： H01L29/68 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/1095 ,  H01L29/7395

摘要： An insulated gate type bipolar-transistor (IGBT) incorporates an excess voltage protecting function and drain voltage fixing function in a monolithic structure. Impurity concentration ND and the thickness of an n.sup.- type drain layer (3) is set so that a depletion region propagating from a p type base layer (7) reaches a p.sup.+ type drain layer at a voltage (V.sub.DSP) lower than a voltage (V.sub.DSS) at which avalanche breakdown is caused within the IGBT element when voltage is applied between the source and the drain.

摘要翻译： 绝缘栅型双极晶体管（IGBT）在整体结构中包含过电压保护功能和漏极电压固定功能。 杂质浓度ND和n型漏极层（3）的厚度被设定为使得从ap型基极层（7）传播的耗尽区域在低于电压（VDSS）的VDSP下达到p +型漏极层 ），当在源极和漏极之间施加电压时，在IGBT元件内引起雪崩击穿。

公开(公告)号：US5448092A

公开(公告)日：1995-09-05

申请号：US70362

申请日：1993-06-01

申请人： Naoto Okabe ,  Norihito Tokura

发明人： Naoto Okabe ,  Norihito Tokura

IPC分类号： H01L29/78 ,  H01L27/02 ,  H01L27/04 ,  H01L29/10 ,  H01L29/739 ,  H01L29/76 ,  H01L29/00 ,  H01L29/74

CPC分类号： H01L29/7395 ,  H01L27/0248 ,  H01L29/1095

摘要： An insulated gate bipolar transistor (IGBT) element has a current detection function. An impurity-diffused area is formed at an area different from a unit cell area on the surface of the element. The current detection is performed by detecting a voltage drop due to carriers flowing in the lateral resistance of the impurity-diffused area. For example, in an n-channel IGBT, electrons are injected from a source electrode through an n-type source layer and the channel to an n-type drain layer at the cell when the unit cell is in an on-state. The pn junction at the drain side is forwardly biased to inject holes from the p-type drain layer to the n-type drain layer. At this time, the electrons also flow to the lower side of the p-type impurity-diffused area provided as the detection portion. Thus, the hole injection occurs at this portion. These surplus holes are discharged through the p-type layer of the detection portion to the source electrode. A potential which corresponds to a product of the lateral resistance of the p-type layer and a hole current appears at the source potential. By detecting this potential and converting the detected potential, an element current can be detected.

摘要翻译： PCT No.PCT / JP92 / 01239 Sec。 371日期：1993年6月1日 102（e）日期1993年6月1日PCT 1992年9月28日PCT公布。 出版物WO93 / 07645 日期：1993年04月15日。绝缘栅双极晶体管（IGBT）元件具有电流检测功能。 在与元件表面上的单元电池区域不同的区域上形成杂质扩散区域。 通过检测由于在杂质扩散区域的横向电阻中流动的载流子的电压降而进行电流检测。 例如，在n沟道IGBT中，当单位电池处于导通状态时，电子从源电极通过n型源极层和沟道注入到单元的n型漏极层。 漏极侧的pn结被向前偏置以从p型漏极层向n型漏极层注入空穴。 此时，电子也流到作为检测部设置的p型杂质扩散区域的下侧。 因此，在该部分发生空穴注入。 这些剩余的孔通过检测部的p型层被排出到源电极。 对应于p型层的横向电阻和空穴电流的乘积的电位出现在电位电位。 通过检测该电位并转换检测到的电位，可以检测元件电流。

公开(公告)号：US4985743A

公开(公告)日：1991-01-15

申请号：US221354

申请日：1988-07-19

申请人： Norihito Tokura ,  Hiroyasu Ito ,  Naoto Okabe

发明人： Norihito Tokura ,  Hiroyasu Ito ,  Naoto Okabe

IPC分类号： H01L29/78 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/45 ,  H01L29/68 ,  H01L29/739

CPC分类号： H01L29/0847 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/7395

摘要： This invention is basically related to an insulated gate bipolar transistor comprising a first conductivity type semiconductor substrate, a second conductivity type semiconductor layer formed on the substrate and having a low concentration of impurities, a first conductivity type base layer formed on a surface of the semiconductor layer, a second conductivity type source layer formed on the surface of the base layer and having a channel region at at least one end thereof, a gate electrode, a source electrode and a drain electrode, and is characterized in that a voltage dropping portion is provided either inside the source layer or between the source layer and the source electrode. Accordingly an insulated gate bipolar semiconductor transistor having this configuration can prevent a latch up phenomenon caused by a voltage drop in a source layer.

摘要翻译： 本发明基本上涉及一种包括第一导电类型半导体衬底，形成在衬底上并具有低浓度杂质的第二导电类型半导体层的绝缘栅双极晶体管，形成在半导体表面上的第一导电型基极层 层，形成在基层的表面上并在其至少一端具有沟道区的第二导电型源极层，栅电极，源电极和漏电极，其特征在于，降压部分为 提供在源层内部或源层和源电极之间。 因此，具有这种结构的绝缘栅双极半导体晶体管可以防止由源极层中的电压降引起的闭锁现象。

公开(公告)号：US07586151B2

公开(公告)日：2009-09-08

申请号：US11578949

申请日：2005-05-11

申请人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Yasushi Okura ,  Akira Kuroyanagi ,  Norihito Tokura

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7811

摘要： The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.

摘要翻译： 本发明提供了一种绝缘栅半导体器件，其在沟槽底部附近具有浮动区域，并且能够可靠地实现高耐压。 绝缘栅半导体器件100包括电流流过的单元区域和围绕单元区域的端子区域。 半导体器件100还在单元区域中具有多个栅极沟槽21以及端子区域中的多个端子沟槽62。 栅极沟槽21形成为条状，并且端子沟槽62同心地形成。 在半导体器件100中，栅极沟槽21和端子沟槽62以栅极沟槽21的端部和端子沟槽62的侧面之间的间隔均匀的方式定位。 也就是说，栅极沟槽21的长度根据端子沟槽62的拐角的曲率来调节。

公开(公告)号：US20070200138A1

公开(公告)日：2007-08-30

申请号：US11709272

申请日：2007-02-22

申请人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

发明人： Yoshihiko Ozeki ,  Norihito Tokura ,  Yukio Tsuzuki

IPC分类号： H01L29/74

CPC分类号： H01L27/0611 ,  H01L29/7395 ,  H01L29/8611

摘要： A semiconductor device includes: a semiconductor substrate; a IGBT region including a first region on a first surface of the substrate and providing a channel-forming region and a second region on a second surface of the substrate and providing a collector; a diode region including a third region on the first surface and providing an anode or a cathode and a fourth region on the second surface and providing the anode or the cathode; a periphery region including a fifth region on the first surface and a sixth region on the second surface. The first, third and fifth regions are commonly and electrically coupled, and the second, fourth and sixth regions are commonly and electrically coupled with one another.

摘要翻译： 半导体器件包括：半导体衬底; IGBT区域，包括在所述基板的第一表面上的第一区域，并且在所述基板的第二表面上提供沟道形成区域和第二区域，并提供集电体; 二极管区域，包括在第一表面上的第三区域，并在第二表面上提供阳极或阴极和第四区域，并提供阳极或阴极; 外围区域，包括在第一表面上的第五区域和第二表面上的第六区域。 第一，第三和第五区域通常和电耦合，并且第二，第四和第六区域彼此通常电耦合。

公开(公告)号：US6133587A

公开(公告)日：2000-10-17

申请号：US23280

申请日：1998-02-13

申请人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

发明人： Yuichi Takeuchi ,  Takeshi Miyajima ,  Norihito Tokura ,  Hiroo Fuma ,  Toshio Murata ,  Takamasa Suzuki ,  Shoichi Onda

IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/7813 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7838 ,  H01L29/0696

摘要： A n.sup.- -type source region 5 is formed on a predetermined region of the surface layer section of the p-type silicon carbide semiconductor layer 3 of a semiconductor substrate 4. A low-resistance p-type silicon carbide region 6 is formed on a predetermined region of the surface layer section in the p-type silicon carbide semiconductor layer 3. A trench 7 is formed in a predetermined region in the n.sup.+ -type source region 5, which trench 7 passes through the n.sup.+ -type source region 5 and the p-type silicon carbide semiconductor layer 3, reaching the n.sup.- -type silicon carbide semiconductor layer 2. The trench 7 has side walls 7a perpendicular to the surface of the semiconductor substrate 4 and a bottom side 7b parallel to the surface of the semiconductor substrate 4. The hexagonal region surrounded by the side walls 7a of the trench 7 is an island semiconductor region 12. A high-reliability gate insulating film 8 is obtained by forming a gate insulating layer on the side walls 7a which surround the island semiconductor region 12.

摘要翻译： n型源极区5形成在半导体衬底4的p型碳化硅半导体层3的表层部分的预定区域上。低电阻p型碳化硅区6形成在 在p型碳化硅半导体层3中的表层部分的预定区域。沟槽7形成在n +型源极区域5中的预定区域中，沟槽7通过n +型源极区域5，并且 p型碳化硅半导体层3，到达n型碳化硅半导体层2.沟槽7具有垂直于半导体衬底4的表面的侧壁7a和平行于半导体衬底的表面的底侧7b 由沟槽7的侧壁7a包围的六边形区域是岛状半导体区域12.通过在侧壁7a上形成栅极绝缘层，形成高可靠性栅极绝缘膜8， 岛半导体区域12。

公开(公告)号：US6133120A

公开(公告)日：2000-10-17

申请号：US704820

申请日：1996-08-28

申请人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

发明人： Takeshi Miyajima ,  Norihito Tokura ,  Atsuo Fukumoto ,  Hidemitsu Hayashi

IPC分类号： H01L21/205 ,  C30B25/00 ,  C30B25/02 ,  H01L21/04 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L29/12 ,  H01L29/24 ,  H01L29/78 ,  C01B31/36

CPC分类号： H01L29/7813 ,  C30B25/00 ,  C30B25/02 ,  C30B29/36 ,  H01L21/0455 ,  H01L29/66068 ,  H01L29/1608 ,  Y10S438/931

摘要： A p-type silicon carbide semiconductor having a high carrier concentration and activation rate is provided by doping boron as an acceptor impurity in a single crystal silicon carbide. The boron occupies silicon sites in a crystal lattice of the single crystal silicon carbide.

摘要翻译： 通过在单晶碳化硅中掺杂硼作为受主杂质来提供具有高载流子浓度和活化速率的p型碳化硅半导体。 硼占据单晶碳化硅的晶格中的硅位置。