公开(公告)号：US10056463B2

公开(公告)日：2018-08-21

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/786 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/516 ,  H01L27/11585 ,  H01L29/40111 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

公开(公告)号：US20180166444A1

公开(公告)日：2018-06-14

申请号：US15892366

申请日：2018-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/205 ,  H01L29/165 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8258 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

公开(公告)号：US09632115B2

公开(公告)日：2017-04-25

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G01R19/00 ,  G01R31/26

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq_q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq_q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

公开(公告)号：US20170040346A1

公开(公告)日：2017-02-09

申请号：US15296027

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/66 ,  H01L21/308 ,  H01L29/165 ,  H01L29/16 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 一种制造半导体器件的衬底的方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。

公开(公告)号：US20130119479A1

公开(公告)日：2013-05-16

申请号：US13736951

申请日：2013-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Han Hung ,  Tsai-Fu Chen ,  Shyh-Fann Ting ,  Cheng-Tung Huang ,  Kun-Hsien Lee ,  Ta-Kang Lo ,  Tzyy-Ming Cheng

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7848

Abstract: A transistor structure is provided in the present invention. The transistor structure includes: a substrate comprising a N-type well, a gate disposed on the N-type well, a spacer disposed on the gate, a first lightly doped region in the substrate below the spacer, a P-type source/drain region disposed in the substrate at two sides of the gate, a silicon cap layer covering the P-type source/drain region and the first lightly doped region and a silicide layer disposed on the silicon cap layer, and covering only a portion of the silicon cap layer.

Abstract translation: 在本发明中提供一种晶体管结构。 晶体管结构包括：包括N型阱的衬底，设置在N型阱上的栅极，设置在栅极上的间隔物，位于衬垫下方的衬底中的第一轻掺杂区域，P型源极/漏极 位于栅极两侧的衬底中的覆盖P型源/漏区和第一轻掺杂区的硅帽层和设置在硅帽层上的硅化物层，并且仅覆盖硅的一部分 盖层。

公开(公告)号：US20230343379A1

公开(公告)日：2023-10-26

申请号：US17744746

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Tung Huang ,  Jen-Yu Wang ,  Po-Chun Yang ,  Yi-Ting Wu ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Chia-Wei Lee

IPC: G11C11/16

CPC classification number: G11C11/1673

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

公开(公告)号：US20220384523A1

公开(公告)日：2022-12-01

申请号：US17368848

申请日：2021-07-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Yung-Ching Hsieh ,  Po-Chun Yang ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: H01L27/22 ,  H01L43/02

Abstract: A MRAM circuit structure is provided in the present invention, with the unit cell composed of three transistors in series and four MTJs, wherein the junction between first transistor and third transistor is first node, the junction between second transistor and third transistor is second node, and the other ends of first transistor and third transistor are connected to a common source line. First MTJ is connected to second MTJ in series to form a first MTJ pair that connecting to the first node, and third MTJ is connected to fourth MTJ in series to form a second MTJ pair that connecting to the second node.

公开(公告)号：US20220181324A1

公开(公告)日：2022-06-09

申请号：US17677983

申请日：2022-02-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Wei Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yan-Jou Chen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

公开(公告)号：US11018185B1

公开(公告)日：2021-05-25

申请号：US16746974

申请日：2020-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jian-Jhong Chen ,  Po-Chun Yang ,  Jhen-Siang Wu ,  Yung-Ching Hsieh ,  Bo-Chang Li ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes a first magnetic tunneling junction (MTJ) pattern on a substrate, a second MTJ pattern adjacent to the first MTJ pattern, and a third MTJ pattern between the first MTJ pattern and the second MTJ pattern. Preferably, the first MTJ pattern, the second MTJ pattern, and the third MTJ pattern constitute a staggered arrangement.

公开(公告)号：US10651235B1

公开(公告)日：2020-05-12

申请号：US16296225

申请日：2019-03-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ting Wu ,  Jhen-Siang Wu ,  Po-Chun Yang ,  Yung-Ching Hsieh ,  Zong-Sheng Zheng ,  Jian-Jhong Chen ,  Jen-Yu Wang ,  Cheng-Tung Huang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

Abstract: A first MRAM set includes a first transistor and a second transistor. The first transistor includes a first gate structure, a first source/drain doping region and a first common source/drain doping region. The second transistor includes a second gate structure, a second source/drain doping region and the first common source/drain doping region. A second MTJ is disposed on the second transistor. The first common source/drain doping region electrically connects to the second MTJ. A first MTJ is disposed on the first transistor. The sizes of the first MTJ and the second MTJ are different. The second MTJ connects to the first MTJ in series. A bit line electrically connects the first MTJ. A source line electrically connects to the first source/drain doping region and the second source/drain doping region.