公开(公告)号：US20160329400A1

公开(公告)日：2016-11-10

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US12237415B2

公开(公告)日：2025-02-25

申请号：US18234889

申请日：2023-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US20240304705A1

公开(公告)日：2024-09-12

申请号：US18665600

申请日：2024-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chih Chuang ,  Chia-Jong Liu ,  Kuang-Hsiu Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Kai-Hsiang Wang ,  Bing-Yang Jiang ,  Yu-Lin Cheng ,  Chun-Jen Chen ,  Yu-Shu Lin ,  Jhong-Yi Huang ,  Chao-Nan Chen ,  Guan-Ying Wu

IPC: H01L29/66 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/42364

Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on a sidewall of the gate structure, a second spacer on a sidewall of the first spacer, a third spacer on a sidewall of the second spacer, and first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure. Preferably, a part of the second spacer comprises an I-shape, the cap layer includes a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer includes a vertical sidewall connected to the inclined sidewall.

公开(公告)号：US20210287944A1

公开(公告)日：2021-09-16

申请号：US17337446

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.

公开(公告)号：US10510609B2

公开(公告)日：2019-12-17

申请号：US15885834

申请日：2018-02-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Jen Chen ,  Tien-I Wu ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/324 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; forming a mask layer on the first fin-shaped structure; and performing a first anneal process so that the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature.

公开(公告)号：US20190221562A1

公开(公告)日：2019-07-18

申请号：US15880492

申请日：2018-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Yu-Ying Lin ,  Yen-Hsing Chen ,  Chun-Jen Chen ,  Chun-Wei Yu ,  Keng-Jen Lin ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66545

Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure, a cladding layer, and a gate structure. The semiconductor substrate includes fin shaped structures. The isolation structure is disposed between the fin shaped structures. Each of the fin shaped structures includes a first portion disposed above a top surface of the isolation structure and a second portion disposed on the first portion. A width of the second portion is smaller than a width of the first portion. The cladding layer is disposed on the first portion and the second portion of each of the fin shaped structures. The cladding layer includes a curved surface. The gate structure is disposed straddling the fin shaped structures.

公开(公告)号：US09748147B1

公开(公告)日：2017-08-29

申请号：US15214467

申请日：2016-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Li-Wei Feng ,  Li-Chieh Hsu ,  Chun-Jen Chen ,  I-Cheng Hu ,  Tien-I Wu ,  Yu-Shu Lin ,  Neng-Hui Yang

IPC: H01L21/20 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L21/823821 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02661 ,  H01L21/2652 ,  H01L21/3086 ,  H01L21/823807 ,  H01L21/8258

Abstract: A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.

公开(公告)号：US20150170916A1

公开(公告)日：2015-06-18

申请号：US14108369

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tien-Wei Yu ,  Chun-Jen Chen ,  Tsung-Mu Yang ,  Ming-Hua Chang ,  Yu-Shu Lin ,  Chin-Cheng Chien

IPC: H01L21/02

CPC classification number: H01L21/02664 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor process includes the steps of providing a substrate with fin structures formed thereon, performing an epitaxy process to grow an epitaxial structure on each fin structure, forming a conformal cap layer on each epitaxial structure, where adjacent conformal cap layers contact each other, and performing an etching process to separate contacting conformal cap layers.

Abstract translation: 一种半导体工艺包括以下步骤：提供具有在其上形成的鳍结构的衬底，执行外延工艺以在每个鳍结构上生长外延结构，在每个外延结构上形成共形盖层，其中相邻的保形盖层彼此接触，以及 执行蚀刻工艺以分离接触的保形盖层。

公开(公告)号：US20230395719A1

公开(公告)日：2023-12-07

申请号：US18234889

申请日：2023-08-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Tang ,  Chung-Ting Huang ,  Bo-Shiun Chen ,  Chun-Jen Chen ,  Yu-Shu Lin

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L29/66553 ,  H01L21/0245 ,  H01L29/0657 ,  H01L29/6656

Abstract: A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming an epitaxial layer adjacent to the gate structure, and then forming a first cap layer on the epitaxial layer. Preferably, a top surface of the first cap layer includes a curve concave upward and a bottom surface of the first cap layer includes a planar surface higher than a top surface of the substrate.

公开(公告)号：US11121254B2

公开(公告)日：2021-09-14

申请号：US16572568

申请日：2019-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Shiun Chen ,  Chun-Jen Chen ,  Chung-Ting Huang ,  Chi-Hsuan Tang ,  Jhong-Yi Huang ,  Guan-Ying Wu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/08 ,  H01L29/15 ,  H01L29/66

Abstract: A transistor with strained superlattices as source/drain regions includes a substrate. A gate structure is disposed on the substrate. Two superlattices are respectively disposed at two sides of the gate structure and embedded in the substrate. The superlattices are strained. Each of the superlattices is formed by a repeated alternating stacked structure including a first epitaxial silicon germanium and a second epitaxial silicon germanium. The superlattices serve as source/drain regions of the transistor.