公开(公告)号：US20170162450A1

公开(公告)日：2017-06-08

申请号：US15435280

申请日：2017-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  Ching-Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L21/8238 ,  H01L23/535 ,  H01L29/08 ,  H01L29/161 ,  H01L27/11 ,  H01L29/78 ,  H01L21/285 ,  H01L21/768 ,  H01L29/66 ,  H01L27/092 ,  H01L29/16

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor structure includes at least a fin-shaped structure, a gate, a source/drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source/drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source/drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source/drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

公开(公告)号：US20170117150A1

公开(公告)日：2017-04-27

申请号：US15401086

申请日：2017-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

IPC: H01L21/033 ,  H01L21/308

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/0657 ,  H01L29/66553

Abstract: A semiconductor device includes a hard mask layer and a plurality of spacers. The hard mask layer is disposed on a target layer and has a first material and a second material. The spacers are disposed on the hard mask layer, wherein a first portion of the spacers is disposed on the first material, and a second portion of the spacers is disposed on the second material.

公开(公告)号：US09401280B2

公开(公告)日：2016-07-26

申请号：US14288399

申请日：2014-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Duan Quan Liao ,  Wei Cheng ,  Yikun Chen ,  Ching Hwa Tey ,  Xiao Zhong Zhu

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L27/11534

Abstract: A semiconductor process includes the following steps. A first gate is formed on a substrate, wherein the first gate includes a stacked gate on the substrate and a cap on the stacked gate. A spacer material is formed to conformally cover the first gate and the substrate. The spacer material is etched to form a spacer on a side of the first gate and a block on the other side of the first gate corresponding to the side. A material covers the substrate, the block, the first gate and the spacer, wherein the top surface of the material is a flat surface. The block, the spacer and the material are pulled down with the same pulling selectivity so that an assisting gate is formed from the block and a selective gate is formed from the spacer.

Abstract translation: 半导体工艺包括以下步骤。 第一栅极形成在衬底上，其中第一栅极包括衬底上的堆叠栅极和堆叠栅极上的帽。 形成间隔物材料以保形地覆盖第一栅极和衬底。 蚀刻间隔材料以在第一栅极的一侧上形成间隔物，并且在第一栅极的另一侧上对应于侧面的块。 材料覆盖基板，块，第一栅极和间隔件，其中材料的顶表面是平坦的表面。 块，间隔物和材料以相同的拉拔选择性被拉下，使得从块形成辅助栅极，并且由间隔物形成选择栅极。

公开(公告)号：US09331200B1

公开(公告)日：2016-05-03

申请号：US14590008

申请日：2015-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Duan Quan Liao ,  Ye Chao Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/161 ,  H01L29/45

CPC classification number: H01L29/7848 ,  H01L29/161 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66568 ,  H01L29/66636

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; and forming a first epitaxial layer, a second epitaxial layer, and a silicide layer in the substrate adjacent to the gate structure. Preferably, the first epitaxial layer, the second epitaxial layer, and the silicide layer comprise SiGeSn.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底; 以及在与栅极结构相邻的衬底中形成第一外延层，第二外延层和硅化物层。 优选地，第一外延层，第二外延层和硅化物层包括SiGeSn。

公开(公告)号：US20150140800A1

公开(公告)日：2015-05-21

申请号：US14082200

申请日：2013-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  CHING HWA TEY

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。

公开(公告)号：US09023726B1

公开(公告)日：2015-05-05

申请号：US14082200

申请日：2013-11-18

Applicant: United Microelectronics Corp.

Inventor： Wei Cheng ,  Ming Sheng Xu ,  Duan Quan Liao ,  Yikun Chen ,  Ching Hwa Tey

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28132 ,  H01L21/28273 ,  H01L21/823468 ,  H01L27/11524

Abstract: A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少一个第一栅堆叠层和至少一个从衬底上的导电层突出的第二栅堆叠层。 随后，在导电层上形成两个间隔物和保护层，两个间隔物和保护层共同围绕突出的第一栅叠层和突出的第二栅堆叠层。 将两个间隔物和保护层用作掩模以去除导电层的一部分。 之后，取下两个间隔物和保护层。