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    METHOD OF FORMING SEMICONDUCTOR DEVICE
    11.
    发明申请
    METHOD OF FORMING SEMICONDUCTOR DEVICE 有权
    形成半导体器件的方法

    公开(公告)号：US20140315365A1

    公开(公告)日：2014-10-23

    申请号：US13866456

    申请日：2013-04-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Li-Chiang Chen ,  Jiunn-Hsiung Liao ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chieh-Te Chen ,  Shang-Yuan Tsai ,  Ching-Pin Hsu

    IPC: H01L29/423 ,  H01L29/66

    CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/823828 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A method of forming a semiconductor device is provided. At least one gate structure including a dummy gate is formed on a substrate. A contact etch stop layer and a dielectric layer are formed to cover the gate structure. A portion of the contact etch stop layer and a portion of the dielectric layer are removed to expose the top of the gate structure. A dry etching process is performed to remove a portion of the dummy gate of the gate structure. A hydrogenation treatment is performed to the surface of the remaining dummy gate. A wet etching process is performed to remove the remaining dummy gate and thereby form a gate trench.

    Abstract translation: 提供一种形成半导体器件的方法。 在基板上形成包括虚拟栅极的至少一个栅极结构。 形成接触蚀刻停止层和电介质层以覆盖栅极结构。 接触蚀刻停止层的一部分和电介质层的一部分被去除以暴露栅极结构的顶部。 执行干蚀刻处理以去除栅极结构的虚拟栅极的一部分。 对剩余的虚拟栅极的表面进行氢化处理。 执行湿蚀刻处理以去除剩余的虚拟栅极，从而形成栅极沟槽。

    Method of forming a FinFET structure
    12.
    发明授权
    Method of forming a FinFET structure 有权
    形成FinFET结构的方法

    公开(公告)号：US08853015B1

    公开(公告)日：2014-10-07

    申请号：US13863393

    申请日：2013-04-16

    Applicant: United Microelectronics Corp.

    Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

    IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78

    CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

    Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

    Semiconductor device with self-aligned contact and method of manufacturing the same
    13.
    发明授权
    Semiconductor device with self-aligned contact and method of manufacturing the same 有权
    具有自对准接触的半导体器件及其制造方法

    公开(公告)号：US09349812B2

    公开(公告)日：2016-05-24

    申请号：US13902975

    申请日：2013-05-27

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

    IPC: H01L29/417 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/485 ,  H01L29/66

    CPC classification number: H01L29/41775 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0692 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device with a self-aligned contact and a method of manufacturing the same, wherein the method comprises the step of forming a 1st dielectric layer on gate structures, form a self-aligned contact trench between two gate structures, forming an 2nd dielectric layer on the 1st dielectric layer and in the self-aligned contact trench; patterning the 2nd dielectric layer into a 1st portion on the 1st dielectric layer and a 2nd portion filling in the self-aligned contact trench, using the 2nd dielectric layer as a mask to etch the 1st dielectric layer, and forming a metal layer and a self-aligned contact simultaneously in the 1st dielectric layer and in the self-aligned contact trench.

    Abstract translation: 具有自对准接触的半导体器件及其制造方法，其中所述方法包括在栅极结构上形成第一介电层的步骤，在两个栅极结构之间形成自对准接触沟槽，形成第二介电层 在第一电介质层和自对准接触沟槽中; 将第二电介质层图案化为第一介电层上的第一部分，并且使用第二介电层作为掩模来蚀刻第一介电层，并形成金属层和自身的第二部分填充在自对准接触沟槽中 在第一电介质层和自对准接触沟槽中同时进行。

    Manufacturing method for forming a self aligned contact
    15.
    发明授权
    Manufacturing method for forming a self aligned contact 有权
    用于形成自对准接触的制造方法

    公开(公告)号：US08993433B2

    公开(公告)日：2015-03-31

    申请号：US13902977

    申请日：2013-05-27

    Applicant: United Microelectronics Corp.

    Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

    Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露部分金属栅极 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

    NON-PLANAR TRANSISTOR
    16.
    发明申请
    NON-PLANAR TRANSISTOR 有权
    非平面晶体管

    公开(公告)号：US20140367798A1

    公开(公告)日：2014-12-18

    申请号：US14470957

    申请日：2014-08-28

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

    IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06

    CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

    Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

    Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。

    Method for Forming Semiconductor Structure Having Opening
    17.
    发明申请
    Method for Forming Semiconductor Structure Having Opening 审中-公开
    形成具有开口的半导体结构的方法

    公开(公告)号：US20140342553A1

    公开(公告)日：2014-11-20

    申请号：US13893349

    申请日：2013-05-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Yu-Tsung Lai ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816

    Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

    Abstract translation: 根据本发明的一个实施例，提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

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